[myhdl-list] Signal names for verilog conversion of interfaces

[Richard L. <r.w...@gm...>]

Hi, I'm a new user to MyHDL and have hit an issue converting my design to
verilog. The python code structure I'm using is to define bus interface
classes and logic functions to operate exclusively between these
interfaces. When it comes to the generated code I see wire and register
name aliasing where I expected instance-specific names. I managed to
whittle it down to a test case as follows (against version 0.9.0):

#!/usr/bin/env python

# coding=utf-8


import argparse


from myhdl import *


class TestInterface():

    def __init__(self):

        self.a = Signal(bool(0))


def test_logic(i_if, o_if, clk=None):

    #@always(clk.posedge)

    @always_comb

    def logic():

        o_if.a.next = i_if.a

    return logic


def main():

    parser = argparse.ArgumentParser()

    parser.add_argument('-t', '--test', type=int, choices=[1, 2], default=1,
help='test to run')

    args = parser.parse_args()


    clk = Signal(bool(0)) if args.test == 2 else None

    i1, o1, i2, o2 = [TestInterface() for _ in range(4)]

    def iftest_top():

        test_instance1 = test_logic(i1, o1, clk)

        test_instance2 = test_logic(i2, o2, clk)

        return test_instance1, test_instance2

    dts = toVerilog(iftest_top)


if __name__ == "__main__":

    main()

In the first case the names alias:

$ ./iftest.py
** ToVerilogWarning: Signal is not driven: i_if_a
** ToVerilogWarning: Signal is driven but not read: o_if_a
$ iverilog -Wall -t null iftest_top.v
iftest_top.v:16: error: Net ``i_if_a'' has already been declared.
iftest_top.v:17: error: Net ``o_if_a'' has already been declared.
2 error(s) during elaboration.

In the second case with an additional signal passed alongside the names
inferred are unique:

$ ./iftest.py -t 2
** ToVerilogWarning: Signal is not driven: test_instance2_i_if_a
** ToVerilogWarning: Signal is driven but not read: test_instance2_o_if_a
** ToVerilogWarning: Signal is not driven: test_instance1_i_if_a
** ToVerilogWarning: Signal is driven but not read: test_instance1_o_if_a
$ iverilog -Wall -t null iftest_top.v

I can certainly use this alternative as a workaround but I'm curious if
this behaviour is a bug or intentional?

Thanks,

Richard.