Re: [myhdl-list] Conversion error: Type mismatch with earlier assignment

[Guy E. <guy...@gm...>]

>
> Can you share your code? I looked into the relevant section in the MyHDL
> code and then looked for a trace in my RTL code, but the situation where
> that error might occur is very rare.
>
>
I actually run into this issue quite often, probably because of my liberal
use of variables to store intermediate results. Here's a code snippet that
triggers the conversion error:

---
from myhdl import *

def mymodule(clk_i, reset_i, count_o):

    count_r_s = Signal(intbv(0)[32:])

    @always_seq(clk_i.posedge, reset=reset_i)
    def logic():
        count_v = count_r_s[:]
        count_v = count_v + 1
        count_r_s.next = count_v

    @always_comb
    def outputs():
        count_o.next = count_r_s

    return instances()

if __name__ == "__main__":
    clk_i = Signal(bool(0))
    reset_i = ResetSignal(0, active=1, async=False)
    count_o = Signal(intbv(0)[32:])
    toVHDL(mymodule, clk_i, reset_i, count_o)
---

Of course, the fix is to change the second variable assignment to:

count_v[:] = count_v + 1

but this is not necessarily obvious from the error message, especially if
you're new to Python/MyHDL. Also, if the same variable gets assigned many
times same function, it may not always be easy to find the assignment that
overwrites the variable (instead of just its value).

What do you think?

Thanks,
Guy.