[myhdl-list] co-simuation
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[myhdl-list] co-simuation
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From: Edward V. <dev...@sb...> - 2015-08-31 17:26:07
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Hello All, I am testing VHD2VL and trying to test the outputted file ifchain.v with MyHDL & Iverilog co-simulation on a Raspberry Pi 2 B. I created the files and folder vcd https://github.com/develone/raspberrypi2_yocto/tree/master/vhd2vl/examples/tb ifchain myhdl.vpi tb_ifchain.v test_ifchain.py vcd The above files were based on Chris Felton alt.hdl that I had forked and tested on Raspberry Pi 2 B https://github.com/develone/alt.hdl/tree/master/examples/ex2_mathadds/test_verilogs git clone https://github.com/develone/alt.hdl.git cd alt.hdl/examples/ex2_mathadds/test_verilogs/ cp ~/raspberrypi2_yocto/vhd2vl/examples/tb/myhdl.vpi . mkdir vcd python test_mathadds.py This producee the expected output. The output in next few lines below between the *** are to verify GTKWAVE, MyHDL & Iverilog work with a Co-Simulation on Raspberry Pi 2 B. ******************************************************************* python test_mathadds.py compiling ... *iverilog -o mathadds ../myhdl/mm_maths1.v ../bsv/mb_maths1.v ../bsv/mkMaths1.v ../chisel/generated/mc_maths1.v ./tb_mathadds.v cosimulation setup ... VCD info: dumpfile vcd/maths1.vcd opened for output. start (co)simulation ... 33: [ 0, 0] mb 0, mc 0, mm 0 [20] 34: [ 1, 1] mb 20, mc 20, mm 20 [20] 35: [ 1, 1] mb 20, mc 20, mm 20 [20] 36: [ 1, 1] mb 20, mc 20, mm 20 [20] 37: [ 1, 1] mb 20, mc 20, mm 20 [5300] 38: [ 543, -13] mb 5300, mc 5300, mm 5300 [5300] 39: [ 543, -13] mb 5300, mc 5300, mm 5300 [5300] 40: [ 543, -13] mb 5300, mc 5300, mm 5300 [5300] 41: [ 543, -13] mb 5300, mc 5300, mm 5300 [-50] 42: [ -7, 2] mb -50, mc -50, mm -50 [-50] 43: [ -7, 2] mb -50, mc -50, mm -50 [-50] 44: [ -7, 2] mb -50, mc -50, mm -50 [-50] 45: [ -7, 2] mb -50, mc -50, mm -50 [630010] 46: [ 31000, 32001] mb -25350, mc -25350, mm -25350 [630010] 47: [ 31000, 32001] mb -25350, mc -25350, mm -25350 [630010] 48: [ 31000, 32001] mb -25350, mc -25350, mm -25350 [630010] In addition the gtkwave vcd/maths1.vcd shows the expected signal changes ******************************************************************* If in stimlus section of test_ifchain.py. I comment the lines 25 & 26 I get the results below. python test_ifchain.py Running test... 0 *{'a': Signal(intbv(0L)), 'status': Signal(False), 'b': Signal(intbv(0L)), compiling ... iverilog -o ifchain ../ifchain.v ./tb_ifchain.v cosimulation setup ... vvp -m ./myhdl.vpi ifchain VCD info: dumpfile vcd/ifchain1.vcd opened for output. <myhdl._Cosimulation.Cosimulation object at 0x769f6870> back from prep cosim start (co)simulation ... This appears to work okay but when I gtkwave vcd/ifchain1.vcd The signals a,b and clk red and status is yellow. When the I uncomment lines 25 & 26 try send values to the co-simulation. The program does not run to completion but crashes with the following error. File "/usr/lib/python2.7/site-packages/myhdl-1.0dev-py2.7.egg/myhdl/_Waiter.py", line 142, in next clause = next(self.generator) File "test_ifchain.py", line 25, in stimlus a.next = 10 Not be an experienced co-simulation user I asked if anyone can provide me insight into this problem. Thanks in advance. Edward Vidal Jr. e-mail dev...@sb... 915-595-1613 |
