Re: [myhdl-list] Examples of using classes?

[Jeremy H. <jer...@gm...>]

Thanks, I'll take a look!
On Wed, 29 Jul 2015 at 10:18 am Christopher Felton <chr...@gm...>
wrote:

> On 7/28/15 5:50 PM, Jeremy Herbert wrote:
> > Hi Chris,
> >
> > I was thinking of using inheritance in defining interfaces using classes
> > like so:
> >
> > class FIFO(object):
> > ...
> >
> > class AXIFIFO(FIFO):
> > ...
> >
> > class WishboneFIFO(FIFO):
> > ...
> >
> > Or even mixins:
> >
> > class FIFO(object):
> > ...
> >
> > class AXI4SSlaveMixin(object):
> > ...
> >
> > class AXI4SMasterMixin(object):
> > ...
> >
> > class AXIFIFO(FIFO, AXI4SSlaveMixin, AXI4SMasterMixin):
> > ...
> >
> > Does this make sense? I'd basically like to be able to drop the
> > AXI4SSlaveMixin and replace it with WishboneSlaveMixin and have it "just
> > work".
>
> Yes, defining interfaces like this is great and you
> can attach transactors, adapters, etc.
>
> My approached would be to define the interfaces and
> still use a function (myhdl module/component):
>
>      def fifo(stream_in, stream_o):
>          inst_adapter_i = stream_i.adapter() # bus specific to generic
>          inst_adapter_o = stream_o.adapter() # ""
>
>          # add logic ....
>          @always_seq(stream_i.clock.posedge, ...)
>          def rtl_in():
>              if stream_i.valid:
>
>
>      stream_in = AXI4()  # instantiate the specifi bus
>      stream_out = AXI4() # instantiate the specific bus
>      inst_fifo = fifo(stream_in, stream_out)
>
> This is kinda like what I did here:
> https://github.com/cfelton/minnesota/tree/master/mn/system
>
> Regards,
> Chris
>
>
>
>
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