Re: [myhdl-list] Interfaces in hierarchcal way

[Josy B. <jos...@gm...>]

Martin Strubel <hackfin <at> section5.ch> writes:


> Having a deja vu here...
> I've found all the SOPC/Qsys and their Xilinx/Lattice counterparts not
> really friendly for maintenance, so I've ended up with an approach 
based
> on GNU make, kconfig (linux kernel config) and an XML device 
description
> (called DClib/devdesc). Like IP-XACT, but way less complex. Could be
> enhanced to spit out MyHDL (currently, it can only generate VHDL based
> Wishbone-capable SoCs). There's also a graphical tool called 
"kactus2",
> but I haven't looked at it in detail.
> The XML approach turned out to be quite robust and future compatible,
> unlike the known migration nightmares that make you freeze old 
software
> versions in a VM...
> 
> Once hierarchy can be maintained in MyHDL, this might become very
> interesting, due to a vast amount of powerful XML processing tools in
> the Python domain.
> 
> Greetings,
> 
> - Martin

Grüezi Martin,

IP-XACT and XML are total strangers to me ... I'll read up on it.
Thanks for the link on 'kactus2'. My colleague thinks it may be very 
usable, but we need some time to experiment and an electronic engineer 
never has enough time (at least 99% of them). Unfortunately 'kactus2' 
doesn't read Qsys xxx_hw.tcl files, but I'm confident I can rewrite my 
xxx_hw.tcl generator, when I find the time :)

Regards,

Josy