Re: [myhdl-list] Interfaces in hierarchcal way

[Christopher F. <chr...@gm...>]

<snip>
>
> Hi Chris,
>
> I was looking at the interface of the verilog modules, not at the body.
> For axi4s_reg the generated verilog gives:
> --
> module axi4s_reg (
>      clk,
>      rst,
>      ai_valid,
>      ai_data,
>      ai_accept,
>      ao_valid,
>      ao_data,
>      ao_accept
> );
> --
> For axi4_lite_reg the verilog start with:
> --
> module axi4_lite_reg (
>      clk,
>      rst
> );
> --
> So all other ports (defined in a hierarchical interface) are gone... I was
> expecting something like:
> --
> module axi4_lite_reg (
>      clk,
>      rst,
>      aw_ai_valid,
>      aw_ai_data,
>      aw_ai_accept,
>      aw_ao_valid,
>      aw_ao_data,
>      aw_ao_accept,
> ...
>      w_ai_valid,
>      w_ai_data,
>      w_ai_accept,
> ...
> );
> --
>
> Or am I missing something? I expect all signals are used...
>

Sorry for the confusion, yes the ports should exist.

Not sure what happened here?  I looks likes, as you
suspected, with the hierarchical interfaces there
is a top-level port conversion bug.

Regards,
Chris