Re: [myhdl-list] Interfaces in hierarchcal way

[Jos H. <jos...@gm...>]

Christopher Felton <chris.felton <at> gmail.com> writes:
> 
> On 7/6/2015 6:38 AM, Jos Huisken wrote:
> > Hi
> >
> > Suppose we have an AXI4 streamig interface:
> <snip>
> >
> > While trying verilog generation all interface signals disappear.
> 
> Jos,
> 
> When I convert the example you provided the signals
> that are used are preserved the signals that are
> not driven are not converted to the target HDL.
> 
> Example, the first ` <at> always_comb` is converted to:
> 
>      assign ai_accept = ((ao_accept && ao_valid) || accept);
> 
> This is for the first conversion, the second conversion
> converts to:
> 
>      assign aw_ai_accept = ((aw_ao_accept && aw_ao_valid) || aw_accept);
> 
> Both these look correct.  I don't see which *used* signals
> are not being converted?
> 
> Regards,
> Chris
> 

Hi Chris,

I was looking at the interface of the verilog modules, not at the body.
For axi4s_reg the generated verilog gives:
--
module axi4s_reg (
    clk,
    rst,
    ai_valid,
    ai_data,
    ai_accept,
    ao_valid,
    ao_data,
    ao_accept
);
--
For axi4_lite_reg the verilog start with:
--
module axi4_lite_reg (
    clk,
    rst
);
--
So all other ports (defined in a hierarchical interface) are gone... I was
expecting something like:
--
module axi4_lite_reg (
    clk,
    rst,
    aw_ai_valid,
    aw_ai_data,
    aw_ai_accept,
    aw_ao_valid,
    aw_ao_data,
    aw_ao_accept,
...
    w_ai_valid,
    w_ai_data,
    w_ai_accept,
...
);
--

Or am I missing something? I expect all signals are used...

Best regards,
Jos