Re: [myhdl-list] Interfaces in hierarchcal way

[Christopher F. <chr...@gm...>]

On 7/6/2015 6:38 AM, Jos Huisken wrote:
> Hi
>
> Suppose we have an AXI4 streamig interface:
<snip>
>
> While trying verilog generation all interface signals disappear.

Jos,

When I convert the example you provided the signals
that are used are preserved the signals that are
not driven are not converted to the target HDL.

Example, the first `@always_comb` is converted to:

     assign ai_accept = ((ao_accept && ao_valid) || accept);


This is for the first conversion, the second conversion
converts to:

     assign aw_ai_accept = ((aw_ao_accept && aw_ao_valid) || aw_accept);

Both these look correct.  I don't see which *used* signals
are not being converted?

Regards,
Chris