[myhdl-list] Interfaces in hierarchcal way

[Jos H. <jos...@gm...>]

Hi

Suppose we have an AXI4 streamig interface:

class AXI4S:
    '''Interface for AXI4 Streaming protocol
    '''
    def __init__(self, wd = 32):
        self.valid  = Signal(False)
        self.data   = Signal(intbv(0xe5)[wd:])
        self.accept = Signal(True)

Could we define an AXI4_lite interface like?:
--
class AXI4_lite:
    '''Interface for AXI4 Lite protocol, consisting of 5 AXI Stream Channels
    '''
    def __init__(self, wa = 32, wd = 32, wr = 8):
        self.aw = AXI4S(wa)
        self.w  = AXI4S(wd)
        self.ar = AXI4S(wa)
        self.r  = AXI4S(wd)
        self.b  = AXI4S(wr)
--
In fact we obtain the 5 transport channels of an AXI4_lite protocol.


While trying verilog generation all interface signals disappear.
You can try verilog generation for:
--
def axi4s_reg(clk, rst, ai, ao):
    ''' AXI4-Stream register. Not verified.
    '''

    accept = Signal(bool(1))

    @always_comb
    def acc():
        ai.accept.next = (ao.accept and ao.valid) or \
                         accept

    @always_seq(clk.posedge, rst)
    def reg():
        xi = ai.accept and ai.valid
        xo = ao.accept and ao.valid
        if xi:
            ao.data.next = ai.data
        ao.valid.next = xi or (ao.valid and not ao.accept)
        accept.next = (ai.accept and not ai.valid) # or not xi

    return reg, acc
--
for which verilog generation seems OK and:
--
def axi4_lite_reg(clk, rst, ai, ao):
    ''' Pipeline register on each channel
    '''

    # Master -> slave communication
    aw = axi4s_reg(clk, rst, ai.aw, ao.aw)
    w  = axi4s_reg(clk, rst, ai.w,  ao.w)
    ar = axi4s_reg(clk, rst, ai.ar, ao.ar)

    # Slave -> master communication
    r  = axi4s_reg(clk, rst, ao.r, ai.r)
    b  = axi4s_reg(clk, rst, ao.b, ai.b)

    return aw, w, ar, r, b


if __name__ == "__main__":
    clk = Signal(False)
    rst = ResetSignal(0, active=0, async=True)
    ai = AXI4S()
    ao = AXI4S()
    toVerilog(axi4s_reg, clk, rst, ai, ao)
    ai = AXI4_lite()
    ao = AXI4_lite()
    toVerilog(axi4_lite_reg, clk, rst, ai, ao)
--

Thanks,
Jos