Re: [myhdl-list] Mixing MyHDL-generated source with other code

[Ben R. <be...@re...>]

OK.  So I've had a look at the Interface class I have in pyvivado to see
how it could be cleaned up.

Constructor is defined at
https://github.com/benreynwar/pyvivado/blob/91449e67330a053d5089aa4ba10c625cb43efb87/interface.py#L21

I think a bunch of crap could be removed to simplify it.  The important
parts are:

Interface Object
---------------------
wires - A list of wire objects.
name - The name of the module
generic_parameters - Parameters that define module (e.g. generic in VHDL)

Wire Object
----------------
name - Name of the wire
direction - Input or Output
signal_type - A signal type object

SignalType Object
------------------------
Responsible for conversion to and from bit arrays.
Responsible for conversion to and from python objects.
Responsible for generating appropriate signal definitions in VHDL or
Verilog and specifying any package dependencies for the type definition.

The interface and wire objects could just be represented as python
dictionaries since they're so simple.
The signal type object would need to be more complex.  Possibly an object
that would work here already exists in MyHDL.

Is that the kind of direction you were thinking?

I'm not sure what you're referring to with the 'use_std_logic' flag in the
previous email.

On Sun, Jun 14, 2015 at 2:01 AM, Henry Gomersall <he...@ca...> wrote:

> On 14/06/15 06:32, Ben Reynwar wrote:
> > You should be able to take advantage of pyvivado Vivado stuff just by
> > using the `pyvivado.project` module.  You could just use that along
> > with all the V* files that you generated using Veriutils.  The main
> > speedup you get is that the project only gets regenerated if the files
> > have changed, which doesn't make much difference during development
> > but is a big plus when you're running unit tests later.  Still
> > annoyingly slow though!
> >
>
> Yeah, it is crap. There is a huge overhead in doing anything in Vivado -
> all my tests are creating new instances which takes ~7 seconds or so
>
> > If I understand your comments on wrapper generation, you're suggesting
> > something similar to what I'm doing with the interface functions but
> > more formalized.  I could then use that same definition to generate
> > VHDL wrappers or a MyHDL wrapper. Is that correct?
>
> Yeah exactly. Some sort of simple interface language/definition from
> which interface wrappers can be generated. Certainly, it's a common
> problem in myhdl that is in need of a neat solution.
>
> That said, what does the new use_std_logic flag do? Is that per-module?
>
> Cheers,
>
> Henry
>
>
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