Re: [myhdl-list] Constant assignments in co-simulation

[Henry G. <he...@ca...>]

On 05/06/15 12:19, Nikolay Kavaldjiev wrote:
>
> During co-simulation we expect to see the output ports aBit and aByte 
> of the co-simulated module to be assigned values True and 55 
> respectively. However, the values that we actually see are different, 
> False and 0. These are the default values of the signals my_bit and 
> my_byte connected to the co-simulated module.
>
> The Reason
>
> We are not sure what the reason for this problem is, but what causes 
> the problem seams to be a Verilog continuous assignments of type:
>
> assign  OutPort=  CONSTANT

I would have expected the Verilog to work as expected. Does it need a 
bitwidth or something?

What do other simulators do?

Henry