Re: [myhdl-list] Hello World

[Günther S. <gue...@gm...>]

Hi Christopher,
Now i rewrote my code with only the system clock in the
process, and i do not have any timing issues anymore.
Now i can run the 3wire SPI with 1 MHz and get
the correct DEVID of the accelerometer.
i checked in my code:
https://github.com/stangassinger/de0_nano_adxl345
Thanks a lot.

Regards

guenther


Am 26.05.2015 um 16:59 schrieb Christopher Felton:
> On 5/21/2015 5:20 AM, Günther Stangassinger wrote:
>> Hello Christopher,
>> you wrote:
>>
>> "The DEnano has a 50MHz clock, this should be
>> the clock driving all your processes/generators.  Don't
>> use the generated SCLK to clock any internal logic."
>>
>>
>> Can you please tell me the reason for this?
> It is going to be the safest design practice and
> the easiest to guarantee you have met timing.  Even
> with slow clocks it is best to use a single clock
> and a single edge in most cases (there are always
> exceptions).
>
> The Altera Quartus synthesis guide is a reasonable
> reference and will do a better job describing the
> pitfalls than I would in a short response.
>
> See section "Synchronous FPGA Design Practices" on
> page12-2 in the following document and specifically
> "Clocking Schemes" on page 12-7.
> https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/qts/qts_qii51006.pdf
>
> Hope that helps,
> Chris
>
>
>
> ------------------------------------------------------------------------------
> One dashboard for servers and applications across Physical-Virtual-Cloud
> Widest out-of-the-box monitoring support with 50+ applications
> Performance metrics, stats and reports that give you Actionable Insights
> Deep dive visibility with transaction tracing using APM Insight.
> http://ad.doubleclick.net/ddm/clk/290420510;117567292;y
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>