Re: [myhdl-list] VHDL converted ConcatSignal

[Josy B. <jos...@gm...>]

> I started writing this when I noticed that the new (allowing 
constants) 
> ConcatSignal doesn't produce VHDL that coerces a signed intbv signal 
to 
> unsigned such that (at least in Vivado) an error occurs. In producing 
a 
> minimal non-working example, I've noticed some other peculiarities in 
> conversion.
> 
> I say the new ConcatSignal, but it might still be present in the older 
code.
> 
> The following gist gives an example of code causing a problem, along 
> with generated output and my comments:
> 
> https://gist.github.com/hgomersall/cf8a47e7f6929564addd
> 
> The work around for the above is fairly simple and neat (and arguably 
> better as it makes the signedness explicit) by having an interim 
> unsigned signal. This is shown in the second comment of the above 
gist.
> 
> FYI: I get a similar complaint if concat_sig_in is set to be a single 
bit:
> 
> concat_sig_in = ConcatSignal(sig_in(1), intbv(0)[9:])
> 
> in which case I get an error along the lines of "indexed name is not a 
> std_ulogic".

Hello Henry,

Three issues in one :)
1. ShadowSignals are taken from the 'original' Signal, but the VHDL 
conversion takes the names from the top-level function. I guess that 
almost everybody uses the same names in the definition and in the 
instantiations, so this doesn't show up often? See 2.

2. Actually the ShadowSignal(h,l) remembers that the source was signed, 
but the ConcatSignal() doesn't take that into account. The fix is quite 
simple. I'm actually working on the new 'std_logic_ports' feature and 
some issues when ShadowSignal is involved. I'll post a PR later tonight.
I have no idea on solving 1. (yet) but will look into that. I'm going to 
do it in several PR's though (or at least in separate commits) 

3. I don't have the issue when taking a subscript instead of a slice, 
and neither should you because a single bit from either a signed or an 
unsigned still is a std_logic.

Regards,

Josy