Re: [myhdl-list] Constant assignments in co-simulation

[Nikolay K. <nik...@gm...>]

Thanks Chris!

I don't think that preserving the combinatorial assignment is my issue,
because the module I have:


def const_assign(aBit, aByte):

    b = Signal(bool(True)) # to avoid "myhdl.AlwaysCombError:
sensitivity list is empty"

    @always_comb
    def logic():
        aBit.next = b
        aByte.next = 0x55

    return logic


Simulates as expected in MyHDL.

Converts to Vorilog as :

module const_assign (
    aBit,
    aByte
);
output aBit;
wire aBit;
output [7:0] aByte;
wire [7:0] aByte;
wire b;
assign b = 1;
assign aBit = b;
assign aByte = 85;

endmodule


Which to me looks OK.

My problem comes when I do co-simulation with Icarus. Then instead of
observing the expected aBit==True and aByte==0x55, I observe aBit==False
and aByte==0, which are the default values of the MyHDL signals connected
co-simulated module.


The problem disappears when I add a dummy print statement in the
"always_comb":

def const_assign(aBit, aByte):

    b = Signal(bool(True)) # to avoid "myhdl.AlwaysCombError:
sensitivity list is empty"

    @always_comb
    def logic():
        aBit.next = b
        aByte.next = 0x55
        print "something"

    return logic


Then the code converts to:

module const_assign (
    aBit,
    aByte
);
output aBit;
reg aBit;
output [7:0] aByte;
reg [7:0] aByte;
wire b;
assign b = 1;

always @(b) begin: CONST_ASSIGN_LOGIC
    aBit = b;
    aByte = 85;
    $write("something");
    $write("\n");
end

endmodule


And in co-simulation I see what I expect: aBit==True and aByte==0x55


It seam to me that the problem I have is related to the interface between
myhdl and icarus and a verilog statement of the type:

assign output_port = some_constant


I am not sure whether this is an issue with my local setup or it is a myhdl
issue. So to check that, can someone using Icarus, please, try to run on
his machine the gist given earlier. It should be only a matter of single
copy/paste and adjusting the path to myhdl.vpi


Regards,

Nikolay


Nikolay Kavaldjiev

E-mail: nik...@gm...
Mobile: +31 641 820 815
Address: Hogewerf 133, 1082NC, Amsterdam, Netherlands
LinkedIn Profile: http://www.linkedin.com/in/kavaldjiev

On 26 May 2015 at 15:43, Christopher Felton <chr...@gm...> wrote:

> On 5/26/2015 7:10 AM, Nikolay Kavaldjiev wrote:
> > Hi All,
> >
> > We have a co-simulation issue: when constants are assigned to signals in
> > co-simulation, the assigned values are not visible in MyHDL.
>
> In the example you linked there are two issues that
> prevent it from working:  first, the initial values
> is not (currently) used in the converted HDL.  The
> `b` Signal in `concat_assign` will not be assigned
> an initial value of `True`.
>
> Second, you can't use and `always_comb` to assign
> a Signal to a constant (as you comments indicate).
>
> >
> > The issue is demonstrated by the following gist:
> > https://gist.github.com/nkavaldj/650fafbc3693f7a501e2
> >
> > The flow we use: MyHDL - > toVerilog -> Icarus
> >
> > Is there a known workaround?
>
> I haven't run into this issue, a workaround would
> be to use the constant directly and not create a
> constant Signal.
>
> Or use a dummy(ies) Signal in the `always_comb`
> to preserve the const assignments.
>
>      d1 = Signal(bool(0))
>      d2 = Signal(bool(0))
>
>      @always_comb
>      def assign():
>         # keep the combinatorial process
>          d2.next = d1
>         # assign constants
>          x1.next = True
>          x2.next = 0x55
>
>      return assign
>
> Or you could use the ROM design pattern:
>
> http://docs.myhdl.org/en/latest/manual/conversion_examples.html#rom-inference
>
> Regards,
> Chris
>
>
>
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