Re: [myhdl-list] Hello World

[Christopher F. <chr...@gm...>]

On 5/21/2015 5:20 AM, Günther Stangassinger wrote:
> Hello Christopher,
> you wrote:
>
> "The DEnano has a 50MHz clock, this should be
> the clock driving all your processes/generators.  Don't
> use the generated SCLK to clock any internal logic."
>
>
> Can you please tell me the reason for this?

It is going to be the safest design practice and
the easiest to guarantee you have met timing.  Even
with slow clocks it is best to use a single clock
and a single edge in most cases (there are always
exceptions).

The Altera Quartus synthesis guide is a reasonable
reference and will do a better job describing the
pitfalls than I would in a short response.

See section "Synchronous FPGA Design Practices" on
page12-2 in the following document and specifically
"Clocking Schemes" on page 12-7.
https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/qts/qts_qii51006.pdf

Hope that helps,
Chris