Re: [myhdl-list] Hello World

[Günther S. <gue...@gm...>]

Hello Christopher,
you wrote:

"The DEnano has a 50MHz clock, this should be
the clock driving all your processes/generators.  Don't
use the generated SCLK to clock any internal logic."


Can you please tell me the reason for this?
Because obviously it is working with when i use the generated SCLK
Is it because of timing issues or are there any other reasons?
I saw in your example that you are using posedge and negedge.
But the frequency of the system clock is so much higher than
the frequency i am working with, so  does it matter  if i use posedge
and in another process negedge.
So i could combine all together in only for example posedge.
Or did i get something wrong?
Thank you.
Regards
guenther






On 27.04.2015 14:38, Christopher Felton wrote:
> On 4/27/2015 12:17 AM, Günther Stangassinger wrote:
>> Thank you very much for your hint.
>> I was trying this.
>> The clock ist now running only when CSn is low.
>> But without success. :-(
>> There is still 0x0 as out put.
>> Does anybody else have any hints?
> There are some changes you should make, in this design
> you should only have a single clock for the internal
> logic.  The DEnano has a 50MHz clock, this should be
> the clock driving all your processes/generators.  Don't
> use the generated SCLK to clock any internal logic.
>
> Then create posedge and negedge strobes based on the
> slower clock (or you can do it vise-versa have state
> machine that creates the edge strobes and the clock
> generated from there).
>
> Here is an example:
> https://bitbucket.org/cfelton/examples/src/tip/mycores/aic23/aic23_spi.py?at=default#cl-96
> http://www.fpgarelated.com/showarticle/41.php
>
>> If you are saying the Tristatesignal is looking ok,
>> than mybe  i should focus on the sequence to read the DEVID.
>> Thank you very much.
> The tristate looks ok in the simulation (not fully
> decoding the bus transaction).  Personally I would
> break out the when/how the tristate is driven to
> a separate process/generator:
>
>       bitout = Signal(bool(0))
>       io = I2C_SDAT.driver()
>
>       # ....
>
>       @always_comb
>       def tristate_driver():
>           if count > 0 and count < 11:
> 	    io.next = None
>           else:
>               io.next = bitout
>
> Only the tristate is the output of this process.
> This shouldn't functionally change your code but in
> the converted code you will have a simple expression
> for the tristate.
>
> Regards,
> Chris
>
>
>
>
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-- 
Mit freundlichen Grüßen
Günther Stangassinger