Re: [myhdl-list] *** Hello World

[Josy B. <jos...@gm...>]

Günther Stangassinger <guenther.stangassinger <at> gmx.net> writes:

> 
> Hello Josy,
> thank you for your answer.
> My problem is that i have to modify the generated verilog(vhdl) code 
to 
> make it work.
> Is myhdl meant to be like this or do i just have bad luck with this 
example?
> I am asking because i am very new to myhdl and this is
> acually my second example what i was trying.
> Are you doing large projects with myhdl?
> I am asking because i want to know if i should
> dig more into myhdl or should i focus more on vhdl, when i do have
> to modify vhdl afterwards anyway.
> So what is your experiance?
> 


Hi Günther,

It is a bit of bad luck, you just hit a bug in the conversion of 
TristateSignal ...

I essentially switched to MyHDL *completely*. For new code, of course I 
have to maintain some 10 years+ of VHDL coding.
Most of my MyHDL modules are components I instantiate inside Qsys, so 
they tend to be not that large (not being small either). However I did a 
quite large project in MyHDL implementing a 'Support Vector Machine' -> 
http://de.wikipedia.org/wiki/Support_Vector_Machine, which produced 6703 
lines of VHDL code.

So yes, use MyHDL. 
One caveat: MyHDL is no silver bullet (there are no silver bullets ...). 
The design of RTL is very close to what you do in either VHDL or 
Verilog. But development is a factor quicker, essentially the simulation 
is where you gain most as you can use full Python to generate data for 
your testbenches and make these self-checking. E.g. in the Support 
Vector Machine module we could import a libsvm library to calculate the 
results to compare our simulation with. And to debug the RTL I wrote an 
integer version of it with lots of output written to the console to 
compare to the signals in the simulation window.
I'm using Eclipse with PyDev for MyHDL editing/running and Impulse to 
view the simulation waveforms (under Windows 8.1)

So once again, MyHDL is definitely preferable over VHDL or Verilog, and 
it is production ready. If a bug however shows up, there is a ready 
community to fix it. I already have a fix for the VHDL (others => 'Z') 
bug, but I have to inspect/fix the Verilog conversion too before I can 
issue a pull request to update the MyHDL 0.9 master development branch.

Regards,

Josy