Re: [myhdl-list] *** GMX Spamverdacht *** Re: *** GMX Spamverdacht *** Hello World

[Josy B. <jos...@gm...>]

Günther Stangassinger <guenther.stangassinger <at> gmx.net> writes:

> 
> Hello,
> it is working:
> https://github.com/stangassinger/de0_nano_adxl345
> I am getting the DEVID 0xE5
> The problem was not the myhdl code.
> The problem was the generated verilog code.
> At the beginning of the generated code where the ports are declared
> it says:
> output I2C_SDAT;
> 
> And this was one and only problem !!
> Because the I2C_SDAT is tristate it should not be a output port.
> There fore i changed it to:
> inout I2C_SDAT;
> 
> And with this change it is working     
> 
> But my question now is:
> How do i have to declare the I2C_SDAT port in myhdl
> so that it generates to "inout" ???
> 
> I declared it with:
> 
> I2C_SDAT = TristateSignal(False)
> 
> What do i have to do the it generates this code:
> inout I2C_SDAT;
> 
> I would be very glad if someone could help me?
> Thank you very much.
> Best regards
> guenther stangassinger
> 
Hallo Günther,

I converted your code to VHDL and there we get an *inout* for I2C_SDAT. 
But there is one error though:
we get :             drive_spi_inst_read_Adr_inst_io <= (others => 'Z');
where it should be:  drive_spi_inst_read_Adr_inst_io <= 'Z';

I suggest you make an issue out of it as the conversion of 
TristateSignal doesn't look to be error-free.

Personally I avoid (read: don't use at all) internal tristate signals: 
my I2C modules have a separate input and output signal for SDa, which I 
then drive to the SDa pin via an **opendrain** primitive in the toplevel 
file.

Regards,

Josy