[myhdl-list] delay of signals

[Edward V. <dev...@sb...>]

Hello All,

In process of creating a FSM to address ram.
I need to store 256 values received
on the USB from the PC.
I then need to extract 3 locations
and write back a result.
for every 3 extractions
(odd and even samples) of column from image.


The version that I initially started can be found at
https://github.com/develone/jpeg-2000-test/blob/master/
ipython_fixbv/test_lifting_jpeg_step/odd_even_fsm.py

Can someone provide some idea how to delay signals in a FSM.
I trie added delay(100) in the FSM which results in 100 ns in the VHDL
file.  
I have two issues that I am trying to fix.
1.) How to delay addr_left, addr_sam, and addr_rht signals to access ram
2.) How to mix addr_left, addr_sam, and addr_rht signals to use a single addr_1
ODD state
addr_left addr_sam addr_rht
0    1    2
    .
    .
252    253    254
EVEN state
addr_left addr_sam addr_rht
1    2    3
    .
    .
253    254    255
Storing the result back for addr_sam.

I am already using a mux found at

https://github.com/develone/jpeg-2000-test/blob/master/ipython_fixbv/test_lifting_jpeg_step/mux.py
To select between ram address when receiving data from the USB and running the
the lifting_step.  I am trying to run this on a XulA2 XC6SXL9.

Any and all help is appreciated.
Thanks




 Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613