Re: [myhdl-list] Mixing MyHDL-generated source with other code

[Ben R. <be...@re...>]

> I think there are at least two clear packages
> here:
>
>     1. the FPGA flow automation
>     2. PLI/VPI less (no FLI) simulator (isim)

Yes, although there is some overlap in the use of the toolchain.  For
example if I want to do a timing simulation, then I would need to use the
appropriate toolchain to do the synthesis and implementation.  I would be
inclined to put the functionality to run a Vivado simulation in the Vivado
toolchain.

Under this model we would have
1. A package for toolchains (or perhaps a package for each toolchain)
2. The FPGA flow automation (making use of the appropriate toolchain)
3. PLI/VPI less simulator (making use of the appropriate toolchain)

The other big area is taking a top level description of the module and
turning that into the files required by the toolchain.
For MyHDL this is straightforward since our top level description is the
top level function along with it's arguments.
For a project that consists of VHDL and Verilog it is straightforward but
tedious to determine what files are required.  If you're using code that
adheres to the hdlmake <http://www.ohwr.org/projects/hdl-make> or fusesoc
<https://github.com/olofk/fusesoc> then things are better since you can
work out dependencies automatically.
If you have a mix of VHDL, Verilog and MyHDL, and perhaps a script to
generate some VHDL then there's no good solution that I've found, which is
why I ended up rolling my own in pyvivado.  I think what we really need is
something like a parameterized package manager than plays nicely with
hdlmake and fusesoc but is flexible enough to allow generated code.


On Thu, May 7, 2015 at 4:12 AM, Christopher Felton <chr...@gm...>
wrote:

> On 5/6/15 12:54 PM, Ben Reynwar wrote:
> > At the moment pyvivado is doing four fairly independent things for me:
> >
> > 1) I use it as a build system to keep track of which modules depend on
> > which other modules and IP blocks and to specify how files that need to
> > be generated are generated.
> > 2) I use it to run python unittests (very similar to what you do with
> > veriutils)
> > 3) I use it to automate Vivado (simulation, synthesis, implementation
> > and deployment)
> > 4) I use it to communicate with the FPGA from python.
> >
> > Things that I don't like about it are:
> > Â  - Doesn't support MyHDL yet.
> > Â  - Tests aren't interactive (i.e. I specify all the inputs and then
> > read all the outputs)
> > Â  - Too many different things rolled into one and more interdependent
> > than they could be.  It should probably be 4 python packages for those
> > 4 purposes.
>
> I think there are at least two clear packages
> here:
>
>      1. the FPGA flow automation
>      2. PLI/VPI less (no FLI) simulator (isim)
>
> It seems your and Henry's work can be combined to
> create the NoFLICosimulation and pyvivado and gizflo
> can be leveraged for the tool-flow automation?
>
> Regards,
> Chris
>
>
>
>
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