Re: [myhdl-list] Mixing MyHDL-generated source with other code

[Christopher F. <chr...@gm...>]

On 5/6/15 12:54 PM, Ben Reynwar wrote:
> At the moment pyvivado is doing four fairly independent things for me:
>
> 1) I use it as a build system to keep track of which modules depend on
> which other modules and IP blocks and to specify how files that need to
> be generated are generated.
> 2) I use it to run python unittests (very similar to what you do with
> veriutils)
> 3) I use it to automate Vivado (simulation, synthesis, implementation
> and deployment)
> 4) I use it to communicate with the FPGA from python.
>
> Things that I don't like about it are:
> Â  - Doesn't support MyHDL yet.
> Â  - Tests aren't interactive (i.e. I specify all the inputs and then
> read all the outputs)
> Â  - Too many different things rolled into one and more interdependent
> than they could be.  It should probably be 4 python packages for those
> 4 purposes.

I think there are at least two clear packages
here:

     1. the FPGA flow automation
     2. PLI/VPI less (no FLI) simulator (isim)

It seems your and Henry's work can be combined to
create the NoFLICosimulation and pyvivado and gizflo
can be leveraged for the tool-flow automation?

Regards,
Chris