Re: [myhdl-list] Mixing MyHDL-generated source with other code

[Henry G. <he...@ca...>]

On 07/05/15 03:19, Christopher Felton wrote:
>> >I like the simulation possibilities provided by MyHDL.
>> >@Ben, are you adding Vivado simulator as a cosimulation option to myhdl?
> I am fairly sure the isim (ISE/Vivado simulator)
> does not support a foreign language interface,
> no PLI/VPI.  You can't do Cosimulation as it is
> done with all other simulators.
>
> Henry (@heng) I believe put together a process to
> create stimulus files, run the simulation, capture
> the outputs, and then read them into the MyHDL and
> validate (I think it went like that).  I believe
> that is the best you can do with isim.
>
> The isim Cosimulation is best kept as a standalone
> package.  Although I haven't tried it, from Henry's
> description it sounds like he has made good progress.
> The isim Cosimulation as a standalone package might
> make sense (i.e using Henry's approach).

Yes, I'm using it on a daily basis now for quite serious code - it's now 
pretty stable with a good test suite. In the confines in which I'm using 
it, i'm very pleased with it.

The build chain at the moment is limited to Vivado, but it's not really 
specific to Vivado - the calling interface is written in templated tcl, 
so a similar one (or indeed any other kind of driver script) could be 
written for other simulators.

It's works in a pretty seamless way - one writes a validated reference 
RTL model and the convertible code. Those can (1) be compared through 
one function to test myhdl RTL correctness (myhdl_cosimulation), which 
can then (2) be switched to another function (vivado_cosimulation) which 
calls Vivado to test the convertible code. The outputs from both the 
vivado run and the reference model are returned.

An example of (1) is given:
e.g. 
https://github.com/hgomersall/Veriutils/blob/master/examples/dsp48e1/test_dsp48e1.py#L188

A test class is then derived from that one that changes the cosimulation 
to use Vivado (i.e. 2) when it's available:
https://github.com/hgomersall/Veriutils/blob/master/examples/dsp48e1/test_dsp48e1.py#L564

Cheers,

Henry