Re: [myhdl-list] Mixing MyHDL-generated source with other code

[Euripedes R. F. <roc...@gm...>]

I'm also interested in have a python package to handle the fpga synthesis
flow, and will try to find some time to colaborate to it in the next weeks.
I think that there's a common structure in the fpga flow and also believe
that is possible to be flexible enough to meet several requirements.

In the last mile every project will need to be composed by a set of
Verilog/VHDL/ngc(?) files. We should go from this idea.

I like the simulation possibilities provided by MyHDL.
@Ben, are you adding Vivado simulator as a cosimulation option to myhdl?



2015-05-06 15:11 GMT-03:00 Christopher Felton <chr...@gm...>:

> <snip>
> >
> > We should probably combine our efforts! What are your goals? So far, the
> > intention has to be quite limited in scope, simply allow a back
> > verification from Vivado, with the motivation driven by the need to
> > allow encrypted IP blocks.
>
> This is probably worth discussion, I have a similar
> project as well that currently supports Quartus
> and ISE, I will push the Vivado when I get a breathe:
>
> https://github.com/cfelton/gizflo
>
> There are 2-3 others that indicated they will be
> contributing.
>
> The question will be, is there a useful project
> structure that meets all our needs?  Or will we
> need to settle with separate projects?
>
> Regards,
> Chris
>
>
>
>
>
>
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