Re: [myhdl-list] Mixing MyHDL-generated source with other code

[Ben R. <be...@re...>]

At the moment pyvivado is doing four fairly independent things for me:

1) I use it as a build system to keep track of which modules depend on
which other modules and IP blocks and to specify how files that need to be
generated are generated.
2) I use it to run python unittests (very similar to what you do with
veriutils)
3) I use it to automate Vivado (simulation, synthesis, implementation and
deployment)
4) I use it to communicate with the FPGA from python.

Things that I don't like about it are:
  - Doesn't support MyHDL yet.
  - Tests aren't interactive (i.e. I specify all the inputs and then read
all the outputs)
  - Too many different things rolled into one and more interdependent than
they could be.  It should probably be 4 python packages for those 4
purposes.

I'm a big fan of combining efforts!  What might be nice would be to take a
step back and think how we could divide stuff up into packages that play
nicely with one another.  For example pyvivado should probably just do (3)
and leave the other stuff to other packages.  We could then have other
packages then automate other toolchains but that provide a similar python
interface.  Perhaps this is a bit ambitious but it's fun thinking about!

On Wed, May 6, 2015 at 12:54 AM, Henry Gomersall <he...@ca...> wrote:

>  On 06/05/15 00:10, Ben Reynwar wrote:
>
> Thanks for that example.
> If I understand correctly this is a MyHDL implementation of a Xilinx DSP
> slice.  When you run a MyHDL cosimulation the tests all use the logic
> defined in that module.  When you run those same tests with a Vivado
> cosimulation, presumably the Xilinx primitive will be used instead.
>
>
> Yes exactly, but the specific module I linked to references a wrapper
> around the primitive, not the primitive itself:
>
> https://github.com/hgomersall/Veriutils/blob/master/vivado/IP/xbip_dsp48_macro_0/dsp48_wrapper.vhd
>
> (not that you should have trivially inferred that).
>
>  I don't quite understand how you're using the vhdl_code property.  I
> thought that the contents of this were placed into the module that was
> being defined, whereas when I look at the VHDL code generated by your
> Vivado cosimulation it looks as if the module has been replaced by that
> code.
>
>  Are you referring to the wrapper? That is a separate piece of code that
> is referenced through the The VHDL code is inserted into the Vivado project
> (in work). The vhdl_code is put into the generated output.
>
>  I also enjoyed looking through veriutils.  You're doing a lot of very
> similar stuff to what I've been doing in pyvivado
> <https://www.github.com/benreynwar/pyvivado>.
>
>
> We should probably combine our efforts! What are your goals? So far, the
> intention has to be quite limited in scope, simply allow a back
> verification from Vivado, with the motivation driven by the need to allow
> encrypted IP blocks.
>
> Cheers,
>
> Henry
>
>
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