Re: [myhdl-list] Mixing MyHDL-generated source with other code

[Henry G. <he...@ca...>]

On 06/05/15 00:10, Ben Reynwar wrote:
> Thanks for that example.
> If I understand correctly this is a MyHDL implementation of a Xilinx 
> DSP slice.  When you run a MyHDL cosimulation the tests all use the 
> logic defined in that module.  When you run those same tests with a 
> Vivado cosimulation, presumably the Xilinx primitive will be used instead.
>

Yes exactly, but the specific module I linked to references a wrapper 
around the primitive, not the primitive itself:
https://github.com/hgomersall/Veriutils/blob/master/vivado/IP/xbip_dsp48_macro_0/dsp48_wrapper.vhd

(not that you should have trivially inferred that).

> I don't quite understand how you're using the vhdl_code property.  I 
> thought that the contents of this were placed into the module that was 
> being defined, whereas when I look at the VHDL code generated by your 
> Vivado cosimulation it looks as if the module has been replaced by 
> that code.
>
Are you referring to the wrapper? That is a separate piece of code that 
is referenced through the The VHDL code is inserted into the Vivado 
project (in work). The vhdl_code is put into the generated output.

> I also enjoyed looking through veriutils.  You're doing a lot of very 
> similar stuff to what I've been doing in pyvivado 
> <https://www.github.com/benreynwar/pyvivado>.

We should probably combine our efforts! What are your goals? So far, the 
intention has to be quite limited in scope, simply allow a back 
verification from Vivado, with the motivation driven by the need to 
allow encrypted IP blocks.

Cheers,

Henry