Re: [myhdl-list] Mixing MyHDL-generated source with other code

[Jan <jen...@mu...>]

On Tue, 5 May 2015 13:23:25 -0700
Ben Reynwar <be...@re...> wrote:

> Hi again,
> 
> One of the things I'm trying to work out as I
> get acquainted with MyHDL is how best to mix
> MyHDL-generated code with existing code.  This
> can be reduced to two basic problems:

[...]

> For (2) I can get close using the
> `vhdl_instance` property but that seems like
> it's more for generating separate VHDL files
> from MyHDL rather than for interfacing with
> non-MyHDL modules.  The things that make this
> difficult to use are that it assumes an
> architecture named 'MyHDL' and that it does not
> allow for generic parameters.  [...]

The following appears to work for RAM
initialisation in verilog, as it is accepted by
the synth tools, the VHDL is obviously broken,
but the technique should work:

def SB_RAM1024x4_cfg(RDATA,RADDR,RCLK,RCLKE,RE,\
  WADDR,WCLK,WCLKE,WDATA,WE, ConfigBits): 
''' sim & synth version of iCE40 block RAM in \
  1024x4 format ''' GSW = 4  #len(WDATA) 
  
  mem=[]
    [... code to build list for simulation]

  @always_comb 
  def ReadLogic(): [...]
  
  @always(WCLK.posedge)
  def WriteLogic(): [...]
  
  # config strings need simple variables #
  CB0x0 = ConfigBits[0x0]
  CB0x1 = ConfigBits[0x1]
    [...]
  CB0xF = ConfigBits[0xF]

__verilog__ = \
"""
SB_RAM1024x4 ram1024x4_01 (
  .RDATA(%(RDATA)s), 
  .RADDR(%(RADDR)s), 
    [...]
  .WE(%(WE)s) 
);   
  
defparam ram1024x4_01.INIT_0 =\
  256'h%(CB0x0)064x; 
defparam ram1024x4_01.INIT_1 =\
  256'h%(CB0x1)064x; 
      [...]
defparam ram1024x4_01.INIT_F =\ 
  256'h%(CB0xF)064x; """

__VHDL__ = \
"""
RAM1024X4: SB_RAM1024x4
generic map(  
  INIT_0 => X"%(CB0x0)064x",
  INIT_1 => X"%(CB0x1)064x",
    [...]
  INIT_F => X"%(CB0xF)064x"   ) 
  
port map (
  RDATA => (%(RDATA)s),
  (%(RADDR)s) => RADDR,
    [...]
  WE => (%(WE)s)  );
"""
    
(I'm about six weeks away from using this in a
design)

Jan Coombs. 
--