Re: [myhdl-list] Mixing MyHDL-generated source with other code

[Ben R. <be...@re...>]

Thanks for that example.
If I understand correctly this is a MyHDL implementation of a Xilinx DSP
slice.  When you run a MyHDL cosimulation the tests all use the logic
defined in that module.  When you run those same tests with a Vivado
cosimulation, presumably the Xilinx primitive will be used instead.

I don't quite understand how you're using the vhdl_code property.  I
thought that the contents of this were placed into the module that was
being defined, whereas when I look at the VHDL code generated by your
Vivado cosimulation it looks as if the module has been replaced by that
code.

I also enjoyed looking through veriutils.  You're doing a lot of very
similar stuff to what I've been doing in pyvivado
<https://www.github.com/benreynwar/pyvivado>.

On Tue, May 5, 2015 at 2:14 PM, Henry Gomersall <he...@ca...> wrote:

> On 05/05/15 21:23, Ben Reynwar wrote:
> > Based on the fact that it's not trival to do this, I'm assuming that
> > most people aren't mixing MyHDL with hand-coded Verilog and VHDL
> > much.  Is there a reason for this?
> >
>
> No, I do it quite a bit. The problem is more that the RTL needs to be
> implemented in MyHDL in order to be useful in that context.
>
> See this:
>
> https://github.com/hgomersall/Veriutils/blob/master/examples/dsp48e1/dsp48e1.py
>
> For an example.
>
> Cheers,
>
> Henry
>
>
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