Re: [myhdl-list] Mixing MyHDL-generated source with other code

[Henry G. <he...@ca...>]

On 05/05/15 21:23, Ben Reynwar wrote:
> Based on the fact that it's not trival to do this, I'm assuming that 
> most people aren't mixing MyHDL with hand-coded Verilog and VHDL 
> much.  Is there a reason for this?
>

No, I do it quite a bit. The problem is more that the RTL needs to be 
implemented in MyHDL in order to be useful in that context.

See this:
https://github.com/hgomersall/Veriutils/blob/master/examples/dsp48e1/dsp48e1.py

For an example.

Cheers,

Henry