[myhdl-list] Mixing MyHDL-generated source with other code

[Ben R. <be...@re...>]

Hi again,

One of the things I'm trying to work out as I get acquainted with MyHDL is
how best to mix MyHDL-generated code with existing code.  This can be
reduced to two basic problems:

1) Be able to generate VHDL/verilog with a predictable interface so it can
used by a non-MyHDL module.
2) Be able to generate VHDL/verilog containing an instantiation of a module
that is not specified by MyHDL.

For (1) it seems to mostly work out of the box.  Sometimes I find that the
`_name` property on the signal has not been forced to match the function
argument name on the top module.  But I'm not sure if that's a bug I've
introduced myself in my local copy.

For (2) I can get close using the `vhdl_instance` property but that seems
like it's more for generating separate VHDL files from MyHDL rather than
for interfacing with non-MyHDL modules.  The things that make this
difficult to use are that it assumes an architecture named 'MyHDL' and that
it does not allow for generic parameters.  The simplest way to get round
this would be to default to not specifying the architecture and interpret a
parameter called 'architecture' to be specifying that.  In a similar manner
a parameter called 'parameters' could be used as the generic parameters.
This would be a small, local change but would add a lot of flexibility.

Based on the fact that it's not trival to do this, I'm assuming that most
people aren't mixing MyHDL with hand-coded Verilog and VHDL much.  Is there
a reason for this?

Cheers,
Ben