Re: [myhdl-list] IP core library
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jandecaluwe
From: Christopher F. <chr...@gm...> - 2015-05-04 15:52:42
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On 5/4/2015 10:37 AM, Euripedes Rocha Filho wrote: > 2015-05-04 12:14 GMT-03:00 Christopher Felton <chr...@gm...>: > >> On 5/3/2015 6:39 AM, Euripedes Rocha Filho wrote: >>> Henry, >>> good articles. >>> >>> @Christopher, >>> I will follow this approach: >>> >>> module.py >>> parameters - named tuple with the parameters/generics for the design >>> interface - class with necessary signals >>> module(parameters, interface) - hdl implementation >>> >> >> For each module I don't think you should force >> everything into one interface for the module. >> In my opinion have logically grouped interfaces: >> >> module(interface1, interface2, ..., parameters) >> >> > The idea is to have some regularity across all modules and in the higher > level you just need: > > import module > > module_interface = module.interface() - An instance of the signals to > interconect > parameters = module.parameters('Parameter') > module_instance = module.module(parameters, interface) But then the regularity doesn't go far? Because each interface will be different? > module_interface = module.interface() This breaks modularity? Don't you want to support different port configurations? Is `module` a class you want to create or just a generic for the example, i.e. import module_xyz? If it is a class shouldn't it be called `Module`? [1] Something I have experimented with is having a default (most commonly used) portmap tied to the module. A default doesn't remove or prevent the modularity based on port types: def somemodule(memmap, streaming, done): # ... somemodule.portmap = {'memmap': Avalon(data_width=64, address_width=32), 'streaming': Streaming(), 'done': Signal(bool(0))} This is a shortcut to the common ports but doesn't prevent: g = somemodule(Avalon(data_width=16, address_width=8), Streamin(), Signal(bool(0)) ) Regards, Chris [1] PEP8 naming suggestions https://www.python.org/dev/peps/pep-0008/#class-names |