Re: [myhdl-list] fixbv to current version of myhdl

[Christopher F. <chr...@gm...>]

On 5/2/15 11:31 AM, Jose M. Gomez Cama wrote:
> Dear Christopher,
>
> You can find the classes and test under my git user, the fork numerics.

Unfortunately, I don't have time to dig through
and figure it out.  I will gladly provide feedback
and my opinions at the appropriate time.

>
> I have done all this work during the last month, but I have had no time
> to make any docs. Sorry for that. In any case, the way it works is
> equivalent to the fixed package in VHDL, so you can use it as a base.
> http://www.eda-stds.org/fphdl/Fixed_ug.pdf

Yes, familiar with it.

>
> I agree with you that it is going to be tough to make an equivalent in
> Verilog, but I do not see a solution that does not provide a resize to
> be useful, at least this is my experience.

I agree a resize is needed, the fixbv will have a
resize.  I can provide a convertible resize now
but I haven't fully embraced the current approach.
I think there is a better option but it will require
and additional enhancement and this enhancement
needs some thought and consideration (other things
have preempted this effort, move to github, GSoC,
...).

I can update the MEP and make it clear the resize
needs to and will exist (put it on my todo list :).
I can outline the current options I envision.  I
wanted to get the `fixbv` type in first and focus
on the resize once the `fixbv` was merged in.

In my opinion, not having a Verilog version is
a show stopper.  It was my goal to learn from
the VHDL fixed-point but not limit the fixbv
from it.

Regards,
Chris