Re: [myhdl-list] fixbv to current version of myhdl

[Jose M. G. C. <ch...@gm...>]

Dear Christopher,

You can find the classes and test under my git user, the fork numerics.

I have done all this work during the last month, but I have had no time to make any docs. Sorry for that. In any case, the way it works is equivalent to the fixed package in VHDL, so you can use it as a base. http://www.eda-stds.org/fphdl/Fixed_ug.pdf

I agree with you that it is going to be tough to make an equivalent in Verilog, but I do not see a solution that does not provide a resize to be useful, at least this is my experience.

In any case, if you have any doubts, feel free to ask and I will give you all the info. But I will not be able to make any docs, at least in a month due to my work, two deadlines in a row.

Best,

Jose M.



> El 02/05/2015, a las 17:47, Christopher Felton <chr...@gm...> escribió:
> 
>> On 5/2/15 10:19 AM, Jose M. Gomez Cama wrote:
>> Dear Edward,
>> 
>> That's the reason for the classes I made, they include the resize an it
>> is fully working.
> 
> Jose,
> 
> If you have some documentation or examples I will
> gladly look at it and provide feedback, otherwise
> your comments are odd and not helpful.
> 
> You can comment on the MEP111 here or review the
> previous mailing-list conversation and provide
> reasonable arguments why you think your approach
> is better than the fixbv approach.  Having to
> create a Verilog version of the VHDL fixed-point
> package to support Verilog conversion is going to
> be a tough sell (IMO).
> 
> Regards,
> Chris
> 
> 
> 
> 
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