Re: [myhdl-list] *** GMX Spamverdacht *** Re: Hello World

[Christopher F. <chr...@gm...>]

On 4/27/2015 12:17 AM, Günther Stangassinger wrote:
> Thank you very much for your hint.
> I was trying this.
> The clock ist now running only when CSn is low.
> But without success. :-(
> There is still 0x0 as out put.
> Does anybody else have any hints?

There are some changes you should make, in this design
you should only have a single clock for the internal
logic.  The DEnano has a 50MHz clock, this should be
the clock driving all your processes/generators.  Don't
use the generated SCLK to clock any internal logic.

Then create posedge and negedge strobes based on the
slower clock (or you can do it vise-versa have state
machine that creates the edge strobes and the clock
generated from there).

Here is an example:
https://bitbucket.org/cfelton/examples/src/tip/mycores/aic23/aic23_spi.py?at=default#cl-96
http://www.fpgarelated.com/showarticle/41.php

> If you are saying the Tristatesignal is looking ok,
> than mybe  i should focus on the sequence to read the DEVID.
> Thank you very much.

The tristate looks ok in the simulation (not fully
decoding the bus transaction).  Personally I would
break out the when/how the tristate is driven to
a separate process/generator:

     bitout = Signal(bool(0))
     io = I2C_SDAT.driver()

     # ....

     @always_comb
     def tristate_driver():
         if count > 0 and count < 11:
	    io.next = None
         else:
             io.next = bitout

Only the tristate is the output of this process.
This shouldn't functionally change your code but in
the converted code you will have a simple expression
for the tristate.

Regards,
Chris