Re: [myhdl-list] *** GMX Spamverdacht *** Re: Hello World

[Günther S. <gue...@gm...>]

Thank you very much for your hint.
I was trying this.
The clock ist now running only when CSn is low.
But without success. :-(
There is still 0x0 as out put.
Does anybody else have any hints?
If you are saying the Tristatesignal is looking ok,
than mybe  i should focus on the sequence to read the DEVID.
Thank you very much.
Regards,
guenther


Am 26.04.2015 um 20:12 schrieb Christopher Felton:
> On 4/26/15 10:45 AM, Günther Stangassinger wrote:
>> Are you sure?
> No, I am not sure.  I am not familiar with 3 wire
> SPI (seems odd) and when I looked at the datasheet,
> quickly ...
>
>> This is not a 4-Wire SPI. It is a 3 wire SPI.
>> For a 4 wire  there are extra ports for reading and writing,
>> but with 3-wire the SDIO-port has the possibility to set a read or a
>> write bit
>> from the accelerometer wich is described here:
>> http://www.geeetech.com/Documents/ADXL345%20Datasheet.pdf
>> And this SDIO-port of the accelerometer is connected with I2C_SDAT of
>> the Altera CyclonIV
> I see (now) that the DE board is only connected
> to support 3-wire SPI or I2C, as you indicated:
> http://www.terasic.com/downloads/cd-rom/de0-nano/
>
> I agree, the tristate is required.
>
>> The problem is, that i do not know wheater i am doing something wrong
>> with the
>> bite sequences, which get into the accelerometer.
>> So i whould very much appreciate, if someone could
>> just run the simulation and take a look at the bitsequence in
>> gtkwave and say if this bit sequence is making sense at all,
>> or i am doing something really strange here?
> I ran you code, something to try is only enable
> the clock during a valid transaction, when CSn is
> low, don't use a free running clock, as shown in
> figure 39:
> http://www.analog.com/media/en/technical-documentation/data-sheets/ADXL345.pdf
>
> Digging through the complete SPI transaction requires
> more time than I have right now.
>
> Regards,
> Chris
>
>
>
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