[myhdl-list] IP core library

[Euripedes R. F. <roc...@gm...>]

Hi,
I'm starting a small (actually no IP so far) library and wondering if
someone has some suggestion on how to structure it.

The repository (just started the package using cookiecutter)
 https://github.com/euripedesrocha/instar

My idea is to use MyHDL as both simulation and hdl decription language,
using verilog conversion to put the design under the regular FPGA work flow
( also I'll use Chistopher's myhdl_tools package in the build flow ).

What I have in mind now is:

There's any advantage in use a class packing the interface signals and a
method with the hardware description, or use another structure?

Any thoughts?