[myhdl-list] Handling signal in cosimulation

[Euripedes R. F. <roc...@gm...>]

After several months I come back, with the same issue now with a better
undersatnding :).

I'm using the following structure to test my VHDL code:

MyHDL->Verilog tb-> VHDL dut

I'm using modelsim with mixed language support and it's working with no
flaws in the last months (the project got frozen for almost an year).

The problem is:

I have some intbv generated in the myhdl test (like in the following code
https://gist.github.com/euripedesrocha/0d162251f9805d23073a )

test_data_correct is the test bench, and build core is a py.test fixture
that build the core once for test session.

The verilog test bench instantiates VHDL code and the internal signals are
all std_logic_vectors. And they are declared as follow

reg
clk_i;

reg
enable_i;

reg signed  [`DATA_WIDTH-1:0]
data_i;

wire
enable_o;

wire signed [`DATA_WIDTH-1:0] data_o;

Every time the generated data is negative the value returned from the VHDL
core is interpreted as a positive number instead of a negative one. All
bits are correct.

Any suggestion for fix it?