Re: [myhdl-list] TypeError: concat: inappropriate argument type: <type 'long'>

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On 04/09/2015 04:14 AM, Jeremy Herbert wrote:
> Hello all,
>
> I'm not qualified to weigh in on any of this, just a note:
>
> Tony, you should perhaps take a look at cocotb. It's in the same
> spirit as myhdl, but specifically for the case of verilog/vhdl for
> the design and Python for the test bench. I use it with modelsim. It
> doesn't generate code however.

That is besides the point here. MyHDL also offers cosimulation
like cocotb (admittedly less developed probably) plus additional
options like convertible testbenches.

The point is that in *any* methdodology, the code should
be debugged by running it / simulating it in a Python
environment.

>
> Thanks, Jeremy On Thu, 9 Apr 2015 at 11:58 am Tony Stark
> <34f...@gm... <mailto:34f...@gm...>> wrote:
>
>>> The only job tasked to MyHDL is to generate the VHDL version of
>>> the testbench described using the MYHDL language.
>>
>> That is complete nonsense. Change your goal and use MyHDL for
>> simulation in the first place, otherwise stop wasting everbody's
>> time.
>
> I read the page you linked to. It is the second time I've read it. I
> also read a few other topics in search of an answer. I agree with the
> concept of a simulation-first design cycle.
>
> I'm guessing the message you were trying to send is that MyHDL uses
> the simulation to verify that the generated code is correct. That's
> great but that's beside the issue here. Let me explain the issue
> again in another way. I want to use Quartus II for synthesis,
> ModelSim SE for simulation, MyHDL only as a possible answer to faster
> VHDL generation, and Sigasi for the final corrections and touch-up.
> In order to do that, MyHDL needs to be able to not only generate the
> VHDL code for a normal entity, but also the testbench for the top
> level entity which is part of a huge VHDL project that it is not
> aware of. The reason this should be perfectly fine is because all it
> has to do with the inherited entity is spit out the port map. It
> doesn't need any knowledge of the entity that has been instantiated
> since all it is required to do is generate VHDL, not simulate it.
>
> To put it in another perspective, lets say I do it the way the design
> of MyHDL is pushing me towards. Lets say I have some huge project
> already written in VHDL. I want to write the testbench for the top
> level entity using MyHDL because I hope that the process of writing
> the code will be faster this way. Now there's a problem. MyHDL
> appears to be designed in such a way that I am forced to write the
> code for the entity I am trying to test to get the VHDL testbench to
> be generated correctly. Now that's a problem because now I'm wasting
> time possibly rewriting the whole project in MyHDL when all I ever
> wanted was just to generate a testbench quickly. Now the potential
> efficiency advantage of MyHDL has just been ruined. Do you see the
> problem here?
>
> On Wed, Apr 8, 2015 at 4:12 PM, Tony Stark <34f...@gm...
> <mailto:34f...@gm...>> wrote:
>
>>> I'm trying to generate a testbench of an entity the MyHDL doesn't
>>> know about and I'm getting a s"ignal not driven" warning along
>>> with the problem of the rest of the signals not showing up in the
>>> conversion.
>>
>> That's because you need to instruct the converter that certain
>> signals are driven because they can't be inferred.
>>
>> I also suspect that your code as written will not do what you want
>> it to do.
>>
>> I imagine you're trying to generate the stimuli in myhdl to drive
>> your VHDL test bench. right?
>>
>> For the device-under-test, you need to create a new factory
>> function (which in your case was called top_level), and set the
>> vhdl_code attribute of that function. You will then need to create
>> a dummy instance as part of that.
>>
>> Then tell the converter how the signals are handled (e.g. driven or
>> read).
>
> I understand what you're saying but it's not what I'm after. I must
> not be explaining myself well. Let me try it again: Image that you
> have created a vhdl entity called "top_level" which was written *only
> in VHDL* (not written in MyHDL). Now imagine you want to write a
> testbench for it, but instead of writing it in VHDL like you did with
> "top_level", you want to save some time and write the testbench using
> MyHDL instead. That's your goal. Now MyHDL will be upset because it
> doesn't know about "top_level" (since it wasn't written in MyHDL).
> That's ok and should be bypassed somehow because you aren't planning
> on using MyHDL for simulation anyway. You want to use ModelSim
> instead. The only job tasked to MyHDL is to generate the VHDL version
> of the testbench described using the MYHDL language.
>
> The code posted in my previous email converts without error but the
> signals and process are left out. There shouldn't be anything more
> than just a very minor edit to force it to leave them in there
> correct?
>
> On Tue, Apr 7, 2015 at 7:38 PM, Tony Stark <34f...@gm...
> <mailto:34f...@gm...>> wrote:
>
> I'm trying to generate a testbench of an entity the MyHDL doesn't
> know about and I'm getting a s"ignal not driven" warning along with
> the problem of the rest of the signals not showing up in the
> conversion.
>
> ***********************************  MyHDL
> *****************************************
>
> from myhdl import *
>
> def top_level_tb(): s_sw = intbv(0)[10] s_clk = Signal(bool(0)) s_btn
> = intbv(0)[3] s_seven_segment_display_1 = intbv(0)[7]
> s_seven_segment_display_0 = intbv(0)[7] s_seven_segment_display_3 =
> intbv(0)[7] s_seven_segment_display_2 = intbv(0)[7] done =
> Signal(bool(0))
>
> top_level_tb.vhdl_code = """ UUT : entity work.top_level port map(
> i_sw                      => s_sw, i_clk                     =>
> s_clk, i_btn                     => s_btn, o_seven_segment_display_1
> => s_seven_segment_display_1, o_seven_segment_display_0 =>
> s_seven_segment_display_0, o_seven_segment_display_3 =>
> s_seven_segment_display_3, o_seven_segment_display_2 =>
> s_seven_segment_display_2 ); """
>
>
> @always(delay(10)) def clkGenerator(): s_clk.next = not s_clk
>
> @always(s_clk.posedge) def stimulus(): s_btn[2].next = 1 delay(40)
> s_btn[2].next = 0 delay(680)
> self.assertEqual(s_seven_segment_display_1, "0100100")
> self.assertEqual(s_seven_segment_display_0, "0100100") delay(680)
> done = 1
>
> return clkGenerator, stimulus
>
> toVHDL(top_level_tb)
>
>
> **************************************  VHDL
> ************************************
>
>
>
> library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all;
> use std.textio.all;
>
> use work.pck_myhdl_081.all;
>
> entity top_level_tb is end entity top_level_tb;
>
>
> architecture MyHDL of top_level_tb is
>
>
>
>
>
> signal s_clk: std_logic;
>
> begin
>
> s_clk <= '0';
>
>
>
>
> UUT : entity work.top_level port map( i_sw                      =>
> s_sw, i_clk                     => s_clk, i_btn
> => s_btn, o_seven_segment_display_1 => s_seven_segment_display_1,
> o_seven_segment_display_0 => s_seven_segment_display_0,
> o_seven_segment_display_3 => s_seven_segment_display_3,
> o_seven_segment_display_2 => s_seven_segment_display_2 );
>
> end architecture MyHDL;
>
> On Tue, Apr 7, 2015 at 6:49 PM, Tony Stark <34f...@gm...
> <mailto:34f...@gm...>> wrote:
>
> I don't understand how the vhdl_code attribute should be used in my
> case. This simple code will generate a VHDL testbench if it weren't
> for the problem of MyHDL not knowing what top_level() is.
>
> def top_level_tb(): s_signalA = intbv(0)[10] s_clk = Signal(bool(0))
>
> # Here is where I need to somehow # tell MyHDL to ignore the fact
> that it doesn't know about top_level() top_level_instance =
> top_level(s_signalA, s_clk)
>
> @always(delay(10)) def clkGenerator(): s_clk.next = not s_clk
>
> @always(s_clk.posedge) def stimulus(): # todo ....
>
> return top_level_instance, clkGenerator, stimulus
>
> toVHDL(top_level_tb)
>
> On Tue, Apr 7, 2015 at 12:36 PM, Tony Stark <34f...@gm...
> <mailto:34f...@gm...>> wrote:
>
>
> Right, I've seen examples like that but what I'm trying to do is
> different. I'm trying to us MyHDL only to generate a testbench in
> VHDL, for an entity not written in MyHDL, for use in modelsim. The
> testbench is for an entity that MyHDL doesn't know about so "dut =
> TimeCount(tens, ones, tenths, startstop, reset, clock)" isn't valid
> since TimeCount() isn't going to exist. In the previous email I made
> a fake one to try to get past that error. MyHDL doesn't actually need
> to know about it since it is not actually testing it. All MyHDL will
> be doing is generating the entity instance declaration like the one
> below so it doesn't need to know about TimeCount() anyway.
>
> UUT : entity work.time_count port map( tens               => s_tens,
> ones            => s_ones, tenths          => s_tenths, startstop
> => s_startstop, reset              => s_reset, clock             =>
> s_clock );
>
> TL;DR I'm trying to us MyHDL only to generate a testbench in VHDL,
> for an entity not written in MyHDL, for use in modelsim. How do I do
> that?
>
> On Apr 4, 2015 7:37 PM, "Tony Stark" <34f...@gm...
> <mailto:34f...@gm...>> wrote:
>
>> Well, the problem there is a python problem. You're trying to
>> import from a module that doesn't exist, or at least not in your
>> path. Again, I suggest that your problems so far are predominantly
>> a lack of understanding of the way Python works, rather than
>> MyHDL.  Beyond that, I don't understand what you're trying to
>> achieve.  Cheers,  Henry
>
> Alright, I've made a little progress on this but still nothing useful
> yet. The VHDL code I've written below is what I want to have MyHDL
> generate. The Python code following that is my attempt at it. It
> generates code without error but it's not nearly useful yet.
>
> ***************************** VHDL
> ***************************************** library ieee; use
> ieee.std_logic_1164.all;
>
> entity top_level_tb is end top_level_tb;
>
> architecture tb of top_level_tb is signal s_sw
> : std_logic_vector(9 downto 0) 	:= (others => '0'); signal s_clk
> : std_logic                   			:= '0'; signal s_btn
> : std_logic_vector(2 downto 0) 	:= (others => '1'); signal
> s_seven_segment_display_1 	: std_logic_vector(6 downto 0) 	:= (others
> => '0'); signal s_seven_segment_display_0 	: std_logic_vector(6
> downto 0) 	:= (others => '0'); signal s_seven_segment_display_3 	:
> std_logic_vector(6 downto 0) 	:= (others => '0'); signal
> s_seven_segment_display_2 	: std_logic_vector(6 downto 0) 	:= (others
> => '0'); signal s_done                    			: std_logic
> := '0'; begin UUT : entity work.top_level port map( i_sw
> => s_sw, i_clk                   				=> s_clk, i_btn
> => s_btn, o_seven_segment_display_1 	=> s_seven_segment_display_1,
> o_seven_segment_display_0 	=> s_seven_segment_display_0,
> o_seven_segment_display_3 	=> s_seven_segment_display_3,
> o_seven_segment_display_2 	=> s_seven_segment_display_2 );
>
> s_clk <= not s_clk and not s_done after 10 ns;
>
> process begin wait for 10 ns; s_btn(2) <= '0';                 --
> reset on wait for 20 ns; s_btn(2) <= '1';                 -- reset
> off
>
> -- <tests to be added here>  --	s_done <= '1'; -- wait; end process;
>
> end tb;
>
> ***************************** MyHDL
> ******************************************
>
> from myhdl import *
>
> # fake entity & fake process created in an attempt to get MyHDL to
> stop complaining about not knowing what top_level() was def
> top_level( i_sw, i_clk, i_btn, o_seven_segment_display_1,
> o_seven_segment_display_0, o_seven_segment_display_3,
> o_seven_segment_display_2 ): s_rst = ResetSignal(0, active=0,
> async=True)
>
> @always_seq(i_clk.posedge, reset=s_rst) def main_process():
> o_seven_segment_display_1 = 0
>
> return main_process
>
> # actual entity of interest def top_level_tb(): s_sw = intbv(0)[10]
> s_clk = Signal(bool(0)) s_btn = intbv(0)[3] s_seven_segment_display_1
> = intbv(0)[7] s_seven_segment_display_0 = intbv(0)[7]
> s_seven_segment_display_3 = intbv(0)[7] s_seven_segment_display_2 =
> intbv(0)[7]
>
> top_level_instance = top_level(s_sw, s_clk, s_btn,
> s_seven_segment_display_1, s_seven_segment_display_0,
> s_seven_segment_display_3, s_seven_segment_display_2)
>
> @always(delay(10)) def clkGenerator(): s_clk.next = not s_clk
>
> @always(s_clk.posedge) def stimulus():  # <more tests to be added
> here>  s_btn[2].next = 0
>
> return top_level_instance, clkGenerator, stimulus
>
> toVHDL(top_level_tb)
>
>
> On Thu, Apr 2, 2015 at 7:31 PM, Tony Stark <34f...@gm...
> <mailto:34f...@gm...>> wrote:
>
> Hi,
>
> I'm getting an error likely due to to a std_logic_vector being much
> monger than myHDL was intended to handle.
>
> addr_array.next = concat(addr_array[436:0],
> most_recent_addr_req_to_sdram -1)
>
> I actually converted VHDL code to pyhton and want to continue
> development of this fifo-like-buffer entity using python, but I need
> to get around this error first.. The reason the array is so large is
> because I want to go through it in one clock cycle if needed. It
> represents 20, 23-bit addresses.
>
> The code is attached. please advise.
>
> Thanks, David
>
>
>
>
>
>
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-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
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