Re: [myhdl-list] TypeError: concat: inappropriate argument type: <type 'long'>

[Chris H. <chr...@po...>]

> On 09 April 2015 at 03:31 Christopher Felton <chr...@gm...> wrote:
>
> I believe the other might have issues with Modelsim
> VHDL Cosim because Modelsim only support FLI for a
> foreign interface and not PLI/VPI (unless that has
> changed recently), In general Verilog Cosim is
> support and VHDL is tricky because only a couple
> simulators use a standard foreign interface (VHPI).

Cadence, Synopsys and Aldec support VHPI; it's only
Mentor who stubbornly refuse to implement the standard.

Cocotb supports VHDL co-simulation in Modelsim/Questa via
the FLI. If you're happy to co-simulate Python that's one
potential route.

I would advise not converting your testbench to VHDL or
Verilog anyway as this puts onerous constraints on your
verification code.  Why not use the full power of Python?

Sticking with MyHDL, another option would be to wrap your
top-level in Verilog and then co-simulate using VPI.

Thanks,

Chris