Re: [myhdl-list] TypeError: concat: inappropriate argument type: <type 'long'>

[Henry G. <he...@ca...>]

On 08/04/15 00:38, Tony Stark wrote:
> I'm trying to generate a testbench of an entity the MyHDL doesn't know 
> about and I'm getting a s"ignal not driven" warning along with the 
> problem of the rest of the signals not showing up in the conversion.

That's because you need to instruct the converter that certain signals 
are driven because they can't be inferred.

I also suspect that your code as written will not do what you want it to 
do.

I imagine you're trying to generate the stimuli in myhdl to drive your 
VHDL test bench. right?

For the device-under-test, you need to create a new factory function 
(which in your case was called top_level), and set the vhdl_code 
attribute of that function. You will then need to create a dummy 
instance as part of that.

Then tell the converter how the signals are handled (e.g. driven or read).

All this is in the documentation, which I suggest you read.

So something like:

def top_level(s_sw, s_clk, s_btn, s_seven_segment_display_1,
               s_seven_segment_display_0, s_seven_segment_display_3,
               s_seven_segment_display_2):

     @instance
     def dummy_instance():
         pass

     top_level.vhdl_code = '''
UUT : entity work.top_level port map(
     i_sw                      => $s_sw,
     i_clk                     => $s_clk,
     i_btn                     => $s_btn,
     o_seven_segment_display_1 => $s_seven_segment_display_1,
     o_seven_segment_display_0 => $s_seven_segment_display_0,
     o_seven_segment_display_3 => $s_seven_segment_display_3,
     o_seven_segment_display_2 => $s_seven_segment_display_2
);
'''

     s_sw.read = True
     s_clk.read = True
     s_btn.read = True
     s_seven_segment_display_0.driven = True
     s_seven_segment_display_1.driven = True
     s_seven_segment_display_2.driven = True
     s_seven_segment_display_3.driven = True

     return dummy_instance

Note the signals are assigned using $signal_name (the vhdl_code 
attribute is a template, not the actual code). This means the converter 
will replace the variable names with the correct VHDL value.

Henry