Re: [myhdl-list] TypeError: concat: inappropriate argument type: <type 'long'>

[Tony S. <34f...@gm...>]

I'm trying to generate a testbench of an entity the MyHDL doesn't know
about and I'm getting a s"ignal not driven" warning along with the problem
of the rest of the signals not showing up in the conversion.

***********************************  MyHDL
*****************************************

from myhdl import *

def top_level_tb():
    s_sw = intbv(0)[10]
    s_clk = Signal(bool(0))
    s_btn = intbv(0)[3]
    s_seven_segment_display_1 = intbv(0)[7]
    s_seven_segment_display_0 = intbv(0)[7]
    s_seven_segment_display_3 = intbv(0)[7]
    s_seven_segment_display_2 = intbv(0)[7]
    done = Signal(bool(0))

    top_level_tb.vhdl_code = """
    UUT : entity work.top_level port map(
            i_sw                      => s_sw,
            i_clk                     => s_clk,
            i_btn                     => s_btn,
            o_seven_segment_display_1 => s_seven_segment_display_1,
            o_seven_segment_display_0 => s_seven_segment_display_0,
            o_seven_segment_display_3 => s_seven_segment_display_3,
            o_seven_segment_display_2 => s_seven_segment_display_2
        );
    """


    @always(delay(10))
    def clkGenerator():
        s_clk.next = not s_clk

    @always(s_clk.posedge)
    def stimulus():
        s_btn[2].next = 1
        delay(40)
        s_btn[2].next = 0
        delay(680)
        self.assertEqual(s_seven_segment_display_1, "0100100")
        self.assertEqual(s_seven_segment_display_0, "0100100")
        delay(680)
        done = 1

    return clkGenerator, stimulus

toVHDL(top_level_tb)


**************************************  VHDL
************************************



library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_081.all;

entity top_level_tb is
end entity top_level_tb;


architecture MyHDL of top_level_tb is





signal s_clk: std_logic;

begin

s_clk <= '0';




    UUT : entity work.top_level port map(
            i_sw                      => s_sw,
            i_clk                     => s_clk,
            i_btn                     => s_btn,
            o_seven_segment_display_1 => s_seven_segment_display_1,
            o_seven_segment_display_0 => s_seven_segment_display_0,
            o_seven_segment_display_3 => s_seven_segment_display_3,
            o_seven_segment_display_2 => s_seven_segment_display_2
        );

end architecture MyHDL;

On Tue, Apr 7, 2015 at 6:49 PM, Tony Stark <34f...@gm...> wrote:

> I don't understand how the vhdl_code attribute should be used in my case.
> This simple code will generate a VHDL testbench if it weren't for the
> problem of MyHDL not knowing what top_level() is.
>
> def top_level_tb():
>     s_signalA = intbv(0)[10]
>     s_clk = Signal(bool(0))
>
>     # Here is where I need to somehow
>     # tell MyHDL to ignore the fact that it doesn't know about top_level()
>     top_level_instance = top_level(s_signalA, s_clk)
>
>     @always(delay(10))
>     def clkGenerator():
>         s_clk.next = not s_clk
>
>     @always(s_clk.posedge)
>     def stimulus():
>         # todo ....
>
>     return top_level_instance, clkGenerator, stimulus
>
> toVHDL(top_level_tb)
>
> On Tue, Apr 7, 2015 at 12:36 PM, Tony Stark <34f...@gm...> wrote:
>
>>
>> Right, I've seen examples like that but what I'm trying to do is
>> different. I'm trying to us MyHDL only to generate a testbench in VHDL, for
>> an entity not written in MyHDL, for use in modelsim. The testbench is for
>> an entity that MyHDL doesn't know about so "dut = TimeCount(tens, ones,
>> tenths, startstop, reset, clock)" isn't valid since TimeCount() isn't going
>> to exist. In the previous email I made a fake one to try to get past that
>> error. MyHDL doesn't actually need to know about it since it is not
>> actually testing it. All MyHDL will be doing is generating the entity
>> instance declaration like the one below so it doesn't need to know about
>> TimeCount() anyway.
>>
>> UUT : entity work.time_count
>>         port map(
>>             tens               => s_tens,
>>             ones            => s_ones,
>>             tenths          => s_tenths,
>>             startstop      => s_startstop,
>>             reset              => s_reset,
>>             clock             => s_clock
>>         );
>>
>> TL;DR I'm trying to us MyHDL only to generate a testbench in VHDL, for an
>> entity not written in MyHDL, for use in modelsim. How do I do that?
>> On Apr 4, 2015 7:37 PM, "Tony Stark" <34f...@gm...> wrote:
>>
>>> >	Well, the problem there is a python problem. You're trying to import
>>> >	from a module that doesn't exist, or at least not in your path. Again, I
>>> >	suggest that your problems so far are predominantly a lack of
>>> >	understanding of the way Python works, rather than MyHDL.
>>> >	
>>> >	Beyond that, I don't understand what you're trying to achieve.
>>> >	
>>> >	Cheers,
>>> >	
>>> >	Henry
>>>
>>> Alright, I've made a little progress on this but still nothing useful yet. The VHDL code I've written below is what I want to have MyHDL generate. The Python code following that is my attempt at it. It generates code without error but it's not nearly useful yet.
>>>
>>> ***************************** VHDL *****************************************
>>> library ieee;
>>> use ieee.std_logic_1164.all;
>>>
>>> entity top_level_tb is
>>> end top_level_tb;
>>>
>>> architecture tb of top_level_tb is
>>> 	signal s_sw                   				: std_logic_vector(9 downto 0) 	:= (others => '0');
>>> 	signal s_clk                     			: std_logic                   			:= '0';
>>> 	signal s_btn                    		 	: std_logic_vector(2 downto 0) 	:= (others => '1');
>>> 	signal s_seven_segment_display_1 	: std_logic_vector(6 downto 0) 	:= (others => '0');
>>> 	signal s_seven_segment_display_0 	: std_logic_vector(6 downto 0) 	:= (others => '0');
>>> 	signal s_seven_segment_display_3 	: std_logic_vector(6 downto 0) 	:= (others => '0');
>>> 	signal s_seven_segment_display_2 	: std_logic_vector(6 downto 0) 	:= (others => '0');
>>> 	signal s_done                    			: std_logic                    			:= '0';
>>> begin
>>> 	UUT : entity work.top_level port map(
>>> 			i_sw                  				=> s_sw,
>>> 			i_clk                   				=> s_clk,
>>> 			i_btn                   				=> s_btn,
>>> 			o_seven_segment_display_1 	=> s_seven_segment_display_1,
>>> 			o_seven_segment_display_0 	=> s_seven_segment_display_0,
>>> 			o_seven_segment_display_3 	=> s_seven_segment_display_3,
>>> 			o_seven_segment_display_2 	=> s_seven_segment_display_2
>>> 		);
>>>
>>> 	s_clk <= not s_clk and not s_done after 10 ns;
>>>
>>> 	process
>>> 	begin
>>> 		wait for 10 ns;
>>> 		s_btn(2) <= '0';                 -- reset on
>>> 		wait for 20 ns;
>>> 		s_btn(2) <= '1';                 -- reset off
>>>
>>> 		-- <tests to be added here>
>>> 		
>>> 		--	s_done <= '1';
>>> 		-- wait;
>>> 	end process;
>>>
>>> end tb;
>>>
>>> ***************************** MyHDL ******************************************
>>>
>>> from myhdl import *
>>>
>>> # fake entity & fake process created in an attempt to get MyHDL to stop complaining about not knowing what top_level() was
>>> def top_level(
>>>         i_sw,
>>>         i_clk,
>>>         i_btn,
>>>         o_seven_segment_display_1,
>>>         o_seven_segment_display_0,
>>>         o_seven_segment_display_3,
>>>         o_seven_segment_display_2
>>> ):
>>>     s_rst = ResetSignal(0, active=0, async=True)
>>>
>>>     @always_seq(i_clk.posedge, reset=s_rst)
>>>     def main_process():
>>>         o_seven_segment_display_1 = 0
>>>
>>>     return main_process
>>>
>>> # actual entity of interest
>>> def top_level_tb():
>>>     s_sw = intbv(0)[10]
>>>     s_clk = Signal(bool(0))
>>>     s_btn = intbv(0)[3]
>>>     s_seven_segment_display_1 = intbv(0)[7]
>>>     s_seven_segment_display_0 = intbv(0)[7]
>>>     s_seven_segment_display_3 = intbv(0)[7]
>>>     s_seven_segment_display_2 = intbv(0)[7]
>>>
>>>     top_level_instance = top_level(s_sw, s_clk, s_btn, s_seven_segment_display_1, s_seven_segment_display_0, s_seven_segment_display_3, s_seven_segment_display_2)
>>>
>>>     @always(delay(10))
>>>     def clkGenerator():
>>>         s_clk.next = not s_clk
>>>
>>>     @always(s_clk.posedge)
>>>     def stimulus():
>>> 		
>>> 		# <more tests to be added here>
>>> 		
>>>         s_btn[2].next = 0
>>>
>>>     return top_level_instance, clkGenerator, stimulus
>>>
>>> toVHDL(top_level_tb)
>>>
>>>
>>> On Thu, Apr 2, 2015 at 7:31 PM, Tony Stark <34f...@gm...> wrote:
>>>
>>>> Hi,
>>>>
>>>> I'm getting an error likely due to to a std_logic_vector being much
>>>> monger than myHDL was intended to handle.
>>>>
>>>> addr_array.next = concat(addr_array[436:0], most_recent_addr_req_to_sdram - 1)
>>>>
>>>> I actually converted VHDL code to pyhton and want to continue
>>>> development of this fifo-like-buffer entity using python, but I need to get
>>>> around this error first..
>>>> The reason the array is so large is because I want to go through it in
>>>> one clock cycle if needed. It represents 20, 23-bit addresses.
>>>>
>>>> The code is attached. please advise.
>>>>
>>>> Thanks,
>>>> David
>>>>
>>>
>>>
>