Re: [myhdl-list] Simulation control

[Henry G. <he...@ca...>]

On 07/04/15 15:56, Juan Pablo Caram wrote:
> The link on "mixed mode" simulation is a proof of concept, but very 
> naive. I've put together a blog post discussing the difficulties that 
> one might find:
>
> http://caram.cl/developing-a-mixed-signal-simulator
>
> The link about interactive simulation is more along the lines of what 
> would be required, but using the function calls, not the interactive 
> console. I see it's using a debugger and that might make it extremely 
> slow. It would be ideal if this functionality was built into the 
> simulator. If I were to implement this functionality into the 
> simulator, any idea on where I should start? I haven't seen any 
> documentation about the operation of the simulator.

I read your blog post, and I still don't see what the fundamental 
problem is.

In your final example, your DAC and your ADC are going to have to be 
instantaneous samplers. It doesn't make any sense otherwise. What does 
it mean to have an event in between clock edges? MyHDL doesn't have any 
concept of signal timings. If the delay means something, you need to 
model that in the analogue side; from the perspective of the RTL model, 
there is some value at some clock edge.

You can model different clock domains, you just have to go the whole hog 
and run each clock domain in a different process. You'll have to define 
your time resolution and have some kind of sync barrier on each 
resolution period (using some kind of meta clock).

That is, on every resolution period, each process will sync with the 
other to keep the simulations timings the same.

I've written a basic example with two clocks here:
https://gist.github.com/hgomersall/6f9268023593ca5fd9d0

I'm pretty sure the synchronisation function isn't doing what it should, 
but that just needs debugging. It might be easier to use Threading, but 
I'm not sure if MyHDL is safe for that (I don't know if there is any 
global shared state).

Cheers,
Henry