Re: [myhdl-list] Simulation control

[Jan C. <th...@mu...>]

On Sun, 5 Apr 2015 18:22:51 -0400
Juan Pablo Caram <jp...@gm...> wrote:

> I don't have a clear idea for the architecture yet, but I suspect it is not
> that simple (or maybe it is)...
> 
> This is what I understand you are referring to:
> 
> def myADC(value):
>   @always(clk.posedge)
>   def logic():
>     value.next = do_things()

I'm doing a CDP1802 processor, and want full debug control to hookup
with software tools. I also wanted it to have the same interface 
whether in simulation or on FPGA. 

Since small cheap FPGA boards generally have a FTDI comm port, the 
interface is based around byte streams.  In simulation the byte stream 
is crudely connected via mmap'd files.  

This allows connection of the hardware or simulation to the support 
tools in other languages, provided it is possible to use mmap in 
those environments, or build a linking module. 

Would any details of this help?

Jan Coombs
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