Re: [myhdl-list] TypeError: concat: inappropriate argument type: <type 'long'>

[Henry G. <he...@ca...>]

On 04/04/15 21:10, Tony Stark wrote:
> 1. How do I receive replies to my questions through email without also 
> receiving emails for any other question posted to the mailing list?

Pay for a support contract? I'm sure several people, likely including 
BDFL Jan, would be willing to offer you the service for a suitable fee.

Otherwise a suitable regex based filter?

>
> 2. I'm unclear on variables. I see how they are declared now but how 
> would I make them retain their value each clock cycle like they do in 
> VHDL instead of reset to zero as you implied? I want to be able to use 
> them for instances where I need the value to change immediately 
> instead of on the next clock cycle, just like they do in VHDL.
>

Like I demonstrated in the example. You're writing valid python, so if 
you assign the variable outside the closure, python scoping rules mean 
it cannot be reassigned inside the closure (an exception will be raised 
if you try), so state is maintained unless explicitly updated. This is 
possible because the type is mutable and so its contents can be modified 
with the [:] slicing operator.

>The second is you're using interim variables like signals (with .next
>and so on). If you want to use interim variables, do so something like:
>
>def foo(signal, clock, reset):
>     my_interim = intbv(0)[10:]
>
>     @always_seq(clock.posedge, reset)
>     def foo_entity():
>         signal.next = my_interim
>         my_interim[:] = my_interim + 1
>
>     return foo_entity


> 3. I'm not sure this code does what was originally intended:
>     addr_array[436:0].next = addr_array[436:0]
>     addr_array[:436].next = most_recent_addr_req_to_sdram - 1
>
>     For a simpler example, lets say cached_addresses is a 
> std_logic_vector representing three, 4-bit addresses put together and 
> has these contents: 0000_0101_1111, and a signal called new_adddress 
> is 4 bits wide, I wanted to shift cached_addresses left 4 bits and 
> make cached_addresses = "0101_1111" & new_adddress. We are basically 
> pushing everything down one spot and adding the new address to the 
> newly opened space. I'm not sure the code above does that..

Crumbs, I might have got the subtleties wrong, but surely you can work 
out how to tweak the example.

How about:
addr_array[436:].next = most_recent_addr_req_to_sdram - 1

Might I suggest learning something about the fundamentals of python - 
slicing and what not.

>
> 4. Is there an example of MyHDL code that generates a VHDL testbench. 
> To clarify, I want to write a testbench in MyHDL for a VHDL entity 
> that MyHDL doesn't know about, and have it immediately generate the 
> VHDL testbench as opposed to MyHDL trying to run it's own simulation 
> of it. So it should be the same process as getting MyHDL to generate a 
> VHDL file for a normal entity excpet it needs to know that this is a 
> testbench so that it doesn't complain about there being no ports 
> declared in the entity being tested. I tried something like this but 
> MyHDL doesn't like it..
>
> from design import *
>
> def top_level_tb():
>     s_sw = Signal(bool(0))
>     s_clk = Signal(bool(0))
>     s_btn = Signal(bool(0))
>     s_seven_segment_display_1 = intbv(0)[7]
>     s_seven_segment_display_0 = intbv(0)[7]
>     s_seven_segment_display_3 = intbv(0)[7]
>     s_seven_segment_display_2 = intbv(0)[7]
>
>     top_level_instance = top_level(top_level, s_sw, s_clk, s_btn, 
> s_seven_segment_display_1, s_seven_segment_display_0, 
> s_seven_segment_display_3, s_seven_segment_display_2)
>
>     @always(delay(10))
>     def clkGenerator():
>         s_clk.next = not s_clk
>
>     @always(clk.posedge)
>     def stimulus():
>         s_btn[2].next = 0
>
>     return top_level_instance, clkGenerator, stimulus
>
> toVHDL(top_level_tb)
>
> which threw:
> "ImportError: No module named design"

Well, the problem there is a python problem. You're trying to import 
from a module that doesn't exist, or at least not in your path. Again, I 
suggest that your problems so far are predominantly a lack of 
understanding of the way Python works, rather than MyHDL.

Beyond that, I don't understand what you're trying to achieve.

Cheers,

Henry