Re: [myhdl-list] TypeError: concat: inappropriate argument type: <type 'long'>

[Tony S. <34f...@gm...>]

I have a few questions now:

1. How do I receive replies to my questions through email without also
receiving emails for any other question posted to the mailing list?

2. I'm unclear on variables. I see how they are declared now but how would
I make them retain their value each clock cycle like they do in VHDL
instead of reset to zero as you implied? I want to be able to use them for
instances where I need the value to change immediately instead of on the
next clock cycle, just like they do in VHDL.

3. I'm not sure this code does what was originally intended:
    addr_array[436:0].next = addr_array[436:0]
    addr_array[:436].next = most_recent_addr_req_to_sdram - 1

    For a simpler example, lets say cached_addresses is a std_logic_vector
representing three, 4-bit addresses put together and has these contents:
0000_0101_1111, and a signal called new_adddress is 4 bits wide, I wanted
to shift cached_addresses left 4 bits and make cached_addresses =
"0101_1111" & new_adddress. We are basically pushing everything down one
spot and adding the new address to the newly opened space. I'm not sure the
code above does that..

4. Is there an example of MyHDL code that generates a VHDL testbench. To
clarify, I want to write a testbench in MyHDL for a VHDL entity that MyHDL
doesn't know about, and have it immediately generate the VHDL testbench as
opposed to MyHDL trying to run it's own simulation of it. So it should be
the same process as getting MyHDL to generate a VHDL file for a normal
entity excpet it needs to know that this is a testbench so that it doesn't
complain about there being no ports declared in the entity being tested. I
tried something like this but MyHDL doesn't like it..

from design import *

def top_level_tb():
    s_sw = Signal(bool(0))
    s_clk = Signal(bool(0))
    s_btn = Signal(bool(0))
    s_seven_segment_display_1 = intbv(0)[7]
    s_seven_segment_display_0 = intbv(0)[7]
    s_seven_segment_display_3 = intbv(0)[7]
    s_seven_segment_display_2 = intbv(0)[7]

    top_level_instance = top_level(top_level, s_sw, s_clk, s_btn,
s_seven_segment_display_1, s_seven_segment_display_0,
s_seven_segment_display_3, s_seven_segment_display_2)

    @always(delay(10))
    def clkGenerator():
        s_clk.next = not s_clk

    @always(clk.posedge)
    def stimulus():
        s_btn[2].next = 0

    return top_level_instance, clkGenerator, stimulus

toVHDL(top_level_tb)

which threw:
"ImportError: No module named design"



>On 03/04/15 00:31, Tony Stark wrote:
>> Hi,
>>
>> I'm getting an error likely due to to a std_logic_vector being much
>> monger than myHDL was intended to handle.
>>
>> addr_array.next = concat(addr_array[436:0], most_recent_addr_req_to_sdram -1)
>> I actually converted VHDL code to pyhton and want to continue
>> development of this fifo-like-buffer entity using python, but I need
>> to get around this error first..
>> The reason the array is so large is because I want to go through it in
>> one clock cycle if needed. It represents 20, 23-bit addresses.
>>
>>
>
>I've created a gist that I think works based on your code...>https://gist.github.com/hgomersall/fc43e4cda49fc2494510 <https://gist.github.com/hgomersall/fc43e4cda49fc2494510>
>
>There seemed to be 2 obvious problems with your code.
>
>The first is concat as you highlighted, not seeming to like values that
>are too long. I suspect this is a problem only in the analyser and can
>be rectified relatively easily? I worked around this by assigning to
>sub-vectors independently.
>
>The second is you're using interim variables like signals (with .next
>and so on). If you want to use interim variables, do so something like:
>
>def foo(signal, clock, reset):
>     my_interim = intbv(0)[10:]
>
>     @always_seq(clock.posedge, reset)
>     def foo_entity():
>         signal.next = my_interim
>         my_interim[:] = my_interim + 1
>
>     return foo_entity
>
>There are two things to pick up on from this: (1) the way in which the
>intbv is updated with the `:` slicing and (2) that my_interim is created
>outside the instance. You can create it inside, but then every time
>foo_entity is run, it will be re initialized to zero (which is not what
>you want?).
>
>The version I've posted goes the other way and turns all your intbv
>interims into signals. This means the timings are all the same (writing
>to an intbv happens now, doing signal.next, nothing changes until next
>time). Effectively a few interim registers are created.
>
>I hope that all makes sense.
>
>Cheers,
>
>Henry


On Thu, Apr 2, 2015 at 7:31 PM, Tony Stark <34f...@gm...> wrote:

> Hi,
>
> I'm getting an error likely due to to a std_logic_vector being much monger
> than myHDL was intended to handle.
>
> addr_array.next = concat(addr_array[436:0], most_recent_addr_req_to_sdram - 1)
>
> I actually converted VHDL code to pyhton and want to continue development
> of this fifo-like-buffer entity using python, but I need to get around this
> error first..
> The reason the array is so large is because I want to go through it in one
> clock cycle if needed. It represents 20, 23-bit addresses.
>
> The code is attached. please advise.
>
> Thanks,
> David
>