[myhdl-list] A VHDL question about signal assignments and delta cycles?

[Henry G. <he...@ca...>]

In the process of writing my verification utilities code, I've 
encountered an interesting situation.

The following gist contains an example VHDL result that I'm querying:
https://gist.github.com/hgomersall/1d02129f02dd209e07cd

It's not a short gist, but it isn't very complicated, and the all the 
question relates to a small section of the code.

In the code the clock is not called clock, but "each_sub_signal" due to 
the way it was generated.

There is a recording block at line 165 onwards that writes to a line to 
a file on every clock edge (i.e. every edge of "each_sub_signal").

As written, this recording block also writes a signal called 
"copied_signal", which is assigned on line 161 just above it, and is 
assigned to be simply "each_sub_signal". That is, according to my 
understanding, it should be the same value as the clock.

Now, when this is run in Vivado, the resultant written file contains the 
values at each edge, and "each_sub_signal" (the clock) is always "1", as 
expected (since we're concerned with the rising edge), and 
"copied_signal" is always "0", implying it hasn't yet been updated.

Is this a delta cycle thing? Is it simulation specific? I'm not too 
concerned about it, but I'd like to understand the reason behind it.

Cheers,

Henry