Re: [myhdl-list] TypeError: concat: inappropriate argument type: <type 'long'>
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From: Henry G. <he...@ca...> - 2015-04-03 08:43:11
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On 03/04/15 00:31, Tony Stark wrote: > Hi, > > I'm getting an error likely due to to a std_logic_vector being much > monger than myHDL was intended to handle. > > addr_array.next = concat(addr_array[436:0], most_recent_addr_req_to_sdram -1) > I actually converted VHDL code to pyhton and want to continue > development of this fifo-like-buffer entity using python, but I need > to get around this error first.. > The reason the array is so large is because I want to go through it in > one clock cycle if needed. It represents 20, 23-bit addresses. > > I've created a gist that I think works based on your code... https://gist.github.com/hgomersall/fc43e4cda49fc2494510 There seemed to be 2 obvious problems with your code. The first is concat as you highlighted, not seeming to like values that are too long. I suspect this is a problem only in the analyser and can be rectified relatively easily? I worked around this by assigning to sub-vectors independently. The second is you're using interim variables like signals (with .next and so on). If you want to use interim variables, do so something like: def foo(signal, clock, reset): my_interim = intbv(0)[10:] @always_seq(clock.posedge, reset) def foo_entity(): signal.next = my_interim my_interim[:] = my_interim + 1 return foo_entity There are two things to pick up on from this: (1) the way in which the intbv is updated with the `:` slicing and (2) that my_interim is created outside the instance. You can create it inside, but then every time foo_entity is run, it will be re initialized to zero (which is not what you want?). The version I've posted goes the other way and turns all your intbv interims into signals. This means the timings are all the same (writing to an intbv happens now, doing signal.next, nothing changes until next time). Effectively a few interim registers are created. I hope that all makes sense. Cheers, Henry |