Re: [myhdl-list] TypeError: Unexpected type

[Christopher F. <chr...@gm...>]

On 3/26/15 2:22 AM, Guy Eschemann wrote:
> The workarounds you showed were actually how my initial code looked
> like. It converted to Verilog without errors, but I got synthesis errors
> because of the variable bounds in the array slices. That's why I wrote
> this ugly if-block which triggered the conversion error.

Yes, it would be a nice addition to detect this case
and flag a warning or use the Verilog-2001 [base += range]
variable part select.

Regards,
Chris