Re: [myhdl-list] TypeError: Unexpected type

[Guy E. <guy...@gm...>]

The workarounds you showed were actually how my initial code looked like.
It converted to Verilog without errors, but I got synthesis errors because
of the variable bounds in the array slices. That's why I wrote this ugly
if-block which triggered the conversion error.

I tried two other workarounds:
> def mpegChannel(clk, rst, s_tx_data_xor_mask_r):
>
>     @always_seq(clk.posedge, reset=rst)
>     def fsm_seq():
>         for i in range(4):
>             s_tx_data_xor_mask_r.next[(i+1)*8:i*8] = i
>
>     return instances()
>
> and:
> def mpegChannel(clk, rst, s_tx_data_xor_mask_r):
>
>     table = tuple([9,8,7,6])
>
>     @always_seq(clk.posedge, reset=rst)
>     def fsm_seq():
>         for i in range(4):
>             s_tx_data_xor_mask_r.next[(i+1)*8:i*8] = table[i]
>
>
>     return instances()
>
> The second allows for any value to be loaded.
> Both convert fine.
>
>