Re: [myhdl-list] Xilinx simulation
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Re: [myhdl-list] Xilinx simulation
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From: Edward V. <dev...@sb...> - 2015-03-25 21:24:57
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Hello All, Continued to try and add instance of matrix_wrap.vhd made manual chg's now do not get errors.The chg's I made are in the file at GitHub."https://github.com/develone/jpeg-2000-test/blob/master/ jpeg2k/parallel_jpeg/chgsto_matrix_wrap_vhd.txt" Should these chg's need to be done or should MyHDL make them? Now, I can map 3 instances of matrix_wrap_lf_u1 matrix_wrap_lf_u1 : matrix_wrap PORT MAP ( flat => flat_lf, z => z_lf, x => x_lf, mrow => mrow_lf, mcol => mcol_lf ); These items were added to tbjp_processvhd.vhd. type t11 is array (0 to 3) of unsigned(9 downto 0); type t1 is array (0 to 3) of t11; signal a : t1:=(others => (others => (others => '0'))); I was hoping a would be a 4 x 4 matrix.This is where I want to put z_lf.These values below are set okay in the simulation. wait for 10 ns; mcol_lf <= "0011"; wait for 10 ns; mrow_lf <= "0011"; wait for 10 ns; x_lf <= "0010100100"; wait for 10 ns; z_lf <= "010100100"; -- a[mrow_lf][mcol_lf] <= z_lf;I can not store z_lf in the matrix a. Regards, Thanks Edward Vidal Jr. e-mail dev...@sb... 915-595-1613 On Wednesday, March 25, 2015 12:24 PM, Edward Vidal <dev...@sb...> wrote: Hello All, I am currently using Xilinx ISE for my simulation.Trying to create a wrapper for flatten.pyCreated "m_flatten_wrap.py". "https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/parallel_jpeg/m_flatten_wrap.py" Having 2 issues when I use m_flatten_wrap.vhd. Line 41: Illegal identifier : mat__flatIf I try and remove 1 of the "_" to make the items mat_flat. Then I get a new error. Line 37: <none> is not declared. Where is None defined? Do I have to add a Library? With the Verilog file I get the Line 30: <None> is not declared. Does my file m_flatten_wrap.py create the error? Regards,Edward Vidal Jr. e-mail dev...@sb... 915-595-1613 On Wednesday, March 25, 2015 6:34 AM, Henry Gomersall <he...@ca...> wrote: On 25/03/15 13:27, Edward Vidal wrote: > release notes. I do have a Zedboard. As of today only the OS is > running. I built the OS using Yocto with the meta-xilinx mailing > list help. Michael Loojimans from Dyplo appears to be one of most > knowledgeable on the FPGA side. Michael help me get sound working > which I needed for VLC. I was able to get several things running > OpenCV, GSL, Java, Python and VLC. I think I would like to work on > face recognition in FPGA, since the Zedboard with OpenCV is a bit > slow. Do not know enough yet to add to the FPGA. What board are you > running? Currently trying to learn MyHDL and ISE using the XuLA2 > board which has XC6SLX9 FPGA. Thanks for the heads up on Vivado. I'm also using a Zedboard - the zedboard license will allow you to use the design edition of Vivado just fine. As an aside, your emails are really hard to read, in particular your code snippets. Can you try just posting in plain text with a liberal sprinkling of carriage returns? Cheers, Henry ------------------------------------------------------------------------------ Dive into the World of Parallel Programming The Go Parallel Website, sponsored by Intel and developed in partnership with Slashdot Media, is your hub for all things parallel software development, from weekly thought leadership blogs to news, videos, case studies, tutorials and more. Take a look and join the conversation now. http://goparallel.sourceforge.net/ _______________________________________________ myhdl-list mailing list myh...@li... https://lists.sourceforge.net/lists/listinfo/myhdl-list |
