Re: [myhdl-list] Xilinx simulation

[Edward V. <dev...@sb...>]

 Hello All,
I am currently using Xilinx ISE for my simulation.Trying to create a wrapper for flatten.pyCreated "m_flatten_wrap.py".
"https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/parallel_jpeg/m_flatten_wrap.py"
Having 2 issues when I use m_flatten_wrap.vhd.
Line 41: Illegal identifier : mat__flatIf I try and remove 1 of the "_" to make the items
mat_flat.
Then I get a new error.
Line 37: <none> is not declared.
Where is None defined?
Do I have to add a Library?
With the Verilog  file I get the Line 30: <None> is not declared.
Does my file m_flatten_wrap.py create the error?
Regards,Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613 


     On Wednesday, March 25, 2015 6:34 AM, Henry Gomersall <he...@ca...> wrote:
   

 On 25/03/15 13:27, Edward Vidal wrote:
> release notes.  I do have a Zedboard.  As of today only the OS is 
> running.  I built the OS using Yocto with the meta-xilinx mailing 
> list  help.  Michael Loojimans from Dyplo appears to be one of most 
> knowledgeable on the FPGA side.  Michael help me get sound working 
> which I needed for VLC.  I was able to get several things running 
> OpenCV, GSL, Java, Python and VLC.  I think I would like to work on 
> face recognition in FPGA, since the Zedboard with OpenCV is a bit 
> slow.  Do not know enough yet to add to the FPGA.  What board are you 
> running?  Currently trying to learn MyHDL and ISE using the XuLA2 
> board which has XC6SLX9 FPGA.  Thanks for the heads up on Vivado.

I'm also using a Zedboard - the zedboard license will allow you to use 
the design edition of Vivado just fine.

As an aside, your emails are really hard to read, in particular your 
code snippets. Can you try just posting in plain text with a liberal 
sprinkling of carriage returns?

Cheers,

Henry